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<div class="textblock"><p>This header file contains identifiers and register-level core functions (or macros) that can be used to access the Xilinx HDMI RX core. </p>
<p>For more information about the operation of this core see the hardware specification and documentation in the higher level driver <a class="el" href="xv__hdmirx_8h.html" title="This is the main header file for Xilinx HDMI RX core. ">xv_hdmirx.h</a> file.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
</p>
<hr/>
<p>
1.00  gm, mg 11/03/15 Initial release.
1.01  MG     30/12/15 Added DDC peripheral HDCP 2.2 masks
1.02  yh     14/01/16 Added Bit Masking for AxisEnable PIO
1.03  MG     18/02/16 Added AUX peripheral error event mask
1.04  MG     13/05/16 Added DDC HDCP mode mask
1.05  MG     27/05/16 Added VTD timebase
1.06  MH     26/07/16 Added DDC HDCP protocol event.
1.07  YH     25/07/16 Used UINTPTR instead of u32 for BaseAddress
                      XV_HdmiRx_WriteReg
                      XV_HdmiRx_ReadReg
1.08  YH     14/11/16 Added BRIDGE_YUV420 and BRIDGE_PIXEL mask to PIO Out
1.09  MMO    02/03/17 Added XV_HDMIRX_VTD_CTRL_SYNC_LOSS_MASK and
                         XV_HDMIRX_VTD_STA_SYNC_LOSS_EVT_MASK for HDCP
                         compliance
2.00  EB     15/11/17 Added XV_HDMIRX_AUX_STA_GCP_CD_EVT_MASK
      YH     16/11/17 Added PIO_IN for bridge overflow interrupt
             16/11/17 Added PIO_OUT for dedicated reset for each clock domain
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ab35e8d251d6f95ff5b39b18eb7b3ef03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab35e8d251d6f95ff5b39b18eb7b3ef03">XV_HDMIRX_HW_H_</a></td></tr>
<tr class="memdesc:ab35e8d251d6f95ff5b39b18eb7b3ef03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#ab35e8d251d6f95ff5b39b18eb7b3ef03">More...</a><br/></td></tr>
<tr class="separator:ab35e8d251d6f95ff5b39b18eb7b3ef03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a03680168612106285110985639ce8aaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a03680168612106285110985639ce8aaf">XV_HDMIRX_VER_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VER_BASE)+(0*4))</td></tr>
<tr class="memdesc:a03680168612106285110985639ce8aaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">VER Identification * Register offset.  <a href="#a03680168612106285110985639ce8aaf">More...</a><br/></td></tr>
<tr class="separator:a03680168612106285110985639ce8aaf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a09dd02e2eec9abeece66f495f3f1624d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a09dd02e2eec9abeece66f495f3f1624d">XV_HDMIRX_VER_VERSION_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VER_BASE)+(1*4))</td></tr>
<tr class="memdesc:a09dd02e2eec9abeece66f495f3f1624d"><td class="mdescLeft">&#160;</td><td class="mdescRight">VER Version Register * offset.  <a href="#a09dd02e2eec9abeece66f495f3f1624d">More...</a><br/></td></tr>
<tr class="separator:a09dd02e2eec9abeece66f495f3f1624d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3072b2f474e183f436eceb634d67a7cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a3072b2f474e183f436eceb634d67a7cf">XV_HDMIRX_PIO_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(0*4))</td></tr>
<tr class="memdesc:a3072b2f474e183f436eceb634d67a7cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Identification register offset.  <a href="#a3072b2f474e183f436eceb634d67a7cf">More...</a><br/></td></tr>
<tr class="separator:a3072b2f474e183f436eceb634d67a7cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1687fd8119ecce7ab4096ff398ba0bb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a1687fd8119ecce7ab4096ff398ba0bb7">XV_HDMIRX_PIO_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(1*4))</td></tr>
<tr class="memdesc:a1687fd8119ecce7ab4096ff398ba0bb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control register offset.  <a href="#a1687fd8119ecce7ab4096ff398ba0bb7">More...</a><br/></td></tr>
<tr class="separator:a1687fd8119ecce7ab4096ff398ba0bb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a489d5aaf485199c1eedcbfea6f4c68ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a489d5aaf485199c1eedcbfea6f4c68ec">XV_HDMIRX_PIO_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(2*4))</td></tr>
<tr class="memdesc:a489d5aaf485199c1eedcbfea6f4c68ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register Set offset.  <a href="#a489d5aaf485199c1eedcbfea6f4c68ec">More...</a><br/></td></tr>
<tr class="separator:a489d5aaf485199c1eedcbfea6f4c68ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afd049a051639c6315d1da85f2c96e1db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#afd049a051639c6315d1da85f2c96e1db">XV_HDMIRX_PIO_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(3*4))</td></tr>
<tr class="memdesc:afd049a051639c6315d1da85f2c96e1db"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register Clear offset.  <a href="#afd049a051639c6315d1da85f2c96e1db">More...</a><br/></td></tr>
<tr class="separator:afd049a051639c6315d1da85f2c96e1db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af1fe9c13a0a5c613a4ca868c82c6f969"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af1fe9c13a0a5c613a4ca868c82c6f969">XV_HDMIRX_PIO_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(4*4))</td></tr>
<tr class="memdesc:af1fe9c13a0a5c613a4ca868c82c6f969"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Register offset.  <a href="#af1fe9c13a0a5c613a4ca868c82c6f969">More...</a><br/></td></tr>
<tr class="separator:af1fe9c13a0a5c613a4ca868c82c6f969"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a21ac38c5488361502fc525c6497e922b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a21ac38c5488361502fc525c6497e922b">XV_HDMIRX_PIO_OUT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(5*4))</td></tr>
<tr class="memdesc:a21ac38c5488361502fc525c6497e922b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register offset.  <a href="#a21ac38c5488361502fc525c6497e922b">More...</a><br/></td></tr>
<tr class="separator:a21ac38c5488361502fc525c6497e922b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add1b42f293960a225e7c7addc81ba41a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#add1b42f293960a225e7c7addc81ba41a">XV_HDMIRX_PIO_OUT_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(6*4))</td></tr>
<tr class="memdesc:add1b42f293960a225e7c7addc81ba41a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register Set offset.  <a href="#add1b42f293960a225e7c7addc81ba41a">More...</a><br/></td></tr>
<tr class="separator:add1b42f293960a225e7c7addc81ba41a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a80d63952308a1e96d3bfd10db732b94c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a80d63952308a1e96d3bfd10db732b94c">XV_HDMIRX_PIO_OUT_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(7*4))</td></tr>
<tr class="memdesc:a80d63952308a1e96d3bfd10db732b94c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register Clear offset.  <a href="#a80d63952308a1e96d3bfd10db732b94c">More...</a><br/></td></tr>
<tr class="separator:a80d63952308a1e96d3bfd10db732b94c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e3ed781e3e5bc38c206ee7d712894c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a7e3ed781e3e5bc38c206ee7d712894c8">XV_HDMIRX_PIO_OUT_MSK_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(8*4))</td></tr>
<tr class="memdesc:a7e3ed781e3e5bc38c206ee7d712894c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Mask Register offset.  <a href="#a7e3ed781e3e5bc38c206ee7d712894c8">More...</a><br/></td></tr>
<tr class="separator:a7e3ed781e3e5bc38c206ee7d712894c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a729bb6c385b324610317135c52298eba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a729bb6c385b324610317135c52298eba">XV_HDMIRX_PIO_IN_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(9*4))</td></tr>
<tr class="memdesc:a729bb6c385b324610317135c52298eba"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Register offset.  <a href="#a729bb6c385b324610317135c52298eba">More...</a><br/></td></tr>
<tr class="separator:a729bb6c385b324610317135c52298eba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab31f69e47fbb9567a8f3f1d1c296899b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab31f69e47fbb9567a8f3f1d1c296899b">XV_HDMIRX_PIO_IN_EVT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(10*4))</td></tr>
<tr class="memdesc:ab31f69e47fbb9567a8f3f1d1c296899b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Register offset.  <a href="#ab31f69e47fbb9567a8f3f1d1c296899b">More...</a><br/></td></tr>
<tr class="separator:ab31f69e47fbb9567a8f3f1d1c296899b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add0c5bcaa9260b976d6ad1b020d59d8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#add0c5bcaa9260b976d6ad1b020d59d8a">XV_HDMIRX_PIO_IN_EVT_RE_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(11*4))</td></tr>
<tr class="memdesc:add0c5bcaa9260b976d6ad1b020d59d8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Rising Edge Register offset.  <a href="#add0c5bcaa9260b976d6ad1b020d59d8a">More...</a><br/></td></tr>
<tr class="separator:add0c5bcaa9260b976d6ad1b020d59d8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae971e0400e365b9f192a1fa190a4b0fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ae971e0400e365b9f192a1fa190a4b0fd">XV_HDMIRX_PIO_IN_EVT_FE_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(12*4))</td></tr>
<tr class="memdesc:ae971e0400e365b9f192a1fa190a4b0fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Falling Edge Register offset.  <a href="#ae971e0400e365b9f192a1fa190a4b0fd">More...</a><br/></td></tr>
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<tr class="memitem:a7b7db301fdc44d8f8252475ed22f6c2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a7b7db301fdc44d8f8252475ed22f6c2f">XV_HDMIRX_PIO_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a7b7db301fdc44d8f8252475ed22f6c2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Run mask.  <a href="#a7b7db301fdc44d8f8252475ed22f6c2f">More...</a><br/></td></tr>
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<tr class="memdesc:a6bda9bcf1d7cf49a93827bf03eea2e4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Interrupt Enable mask.  <a href="#a6bda9bcf1d7cf49a93827bf03eea2e4a">More...</a><br/></td></tr>
<tr class="separator:a6bda9bcf1d7cf49a93827bf03eea2e4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd3c33cf8c70cbeb50a95f7d58556579"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#abd3c33cf8c70cbeb50a95f7d58556579">XV_HDMIRX_PIO_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
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<tr class="separator:abd3c33cf8c70cbeb50a95f7d58556579"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada79d92307e4e82afb7e7e0e477bdb8c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ada79d92307e4e82afb7e7e0e477bdb8c">XV_HDMIRX_PIO_STA_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ada79d92307e4e82afb7e7e0e477bdb8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Event mask.  <a href="#ada79d92307e4e82afb7e7e0e477bdb8c">More...</a><br/></td></tr>
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<tr class="memitem:ae9ededc60f434b8f94a94138d0ae1770"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ae9ededc60f434b8f94a94138d0ae1770">XV_HDMIRX_PIO_OUT_RESET_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
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<tr class="memitem:aebf168954f7f549697220cb79a2db0e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aebf168954f7f549697220cb79a2db0e5">XV_HDMIRX_PIO_OUT_LNK_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
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<tr class="separator:aebf168954f7f549697220cb79a2db0e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5461b9268a85702c01115f85b1e49537"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a5461b9268a85702c01115f85b1e49537">XV_HDMIRX_PIO_OUT_VID_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a5461b9268a85702c01115f85b1e49537"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out video enable mask.  <a href="#a5461b9268a85702c01115f85b1e49537">More...</a><br/></td></tr>
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<tr class="memitem:a51974eaab5f1447924b24e7ad9795f41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a51974eaab5f1447924b24e7ad9795f41">XV_HDMIRX_PIO_OUT_HPD_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a51974eaab5f1447924b24e7ad9795f41"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Hot-Plug Detect mask.  <a href="#a51974eaab5f1447924b24e7ad9795f41">More...</a><br/></td></tr>
<tr class="separator:a51974eaab5f1447924b24e7ad9795f41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaa2244687e75ef859bf959aade976488"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aaa2244687e75ef859bf959aade976488">XV_HDMIRX_PIO_OUT_DEEP_COLOR_MASK</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:aaa2244687e75ef859bf959aade976488"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Deep Color mask.  <a href="#aaa2244687e75ef859bf959aade976488">More...</a><br/></td></tr>
<tr class="separator:aaa2244687e75ef859bf959aade976488"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a415a6510fe5c6bc29230e9c370e13985"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a415a6510fe5c6bc29230e9c370e13985">XV_HDMIRX_PIO_OUT_PIXEL_RATE_MASK</a>&#160;&#160;&#160;0xC0</td></tr>
<tr class="memdesc:a415a6510fe5c6bc29230e9c370e13985"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Rate mask.  <a href="#a415a6510fe5c6bc29230e9c370e13985">More...</a><br/></td></tr>
<tr class="separator:a415a6510fe5c6bc29230e9c370e13985"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad392d4b85c6851c8ab14735efbfb863c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ad392d4b85c6851c8ab14735efbfb863c">XV_HDMIRX_PIO_OUT_SAMPLE_RATE_MASK</a>&#160;&#160;&#160;0x300</td></tr>
<tr class="memdesc:ad392d4b85c6851c8ab14735efbfb863c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Sample Rate mask.  <a href="#ad392d4b85c6851c8ab14735efbfb863c">More...</a><br/></td></tr>
<tr class="separator:ad392d4b85c6851c8ab14735efbfb863c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a03f17ccc9e2953ac921f07446dfc9c16"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a03f17ccc9e2953ac921f07446dfc9c16">XV_HDMIRX_PIO_OUT_COLOR_SPACE_MASK</a>&#160;&#160;&#160;0xC00</td></tr>
<tr class="memdesc:a03f17ccc9e2953ac921f07446dfc9c16"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Space mask.  <a href="#a03f17ccc9e2953ac921f07446dfc9c16">More...</a><br/></td></tr>
<tr class="separator:a03f17ccc9e2953ac921f07446dfc9c16"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1d084bc85a72b35776b604a1f15d24df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a1d084bc85a72b35776b604a1f15d24df">XV_HDMIRX_PIO_OUT_AXIS_EN_MASK</a>&#160;&#160;&#160;0x80000</td></tr>
<tr class="memdesc:a1d084bc85a72b35776b604a1f15d24df"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Axis Enable mask.  <a href="#a1d084bc85a72b35776b604a1f15d24df">More...</a><br/></td></tr>
<tr class="separator:a1d084bc85a72b35776b604a1f15d24df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab370f0d9a89642724e7a1ad311468aff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab370f0d9a89642724e7a1ad311468aff">XV_HDMIRX_PIO_OUT_DEEP_COLOR_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ab370f0d9a89642724e7a1ad311468aff"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Deep Color shift.  <a href="#ab370f0d9a89642724e7a1ad311468aff">More...</a><br/></td></tr>
<tr class="separator:ab370f0d9a89642724e7a1ad311468aff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a93050e6b1ea95d7147823e81113e6919"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a93050e6b1ea95d7147823e81113e6919">XV_HDMIRX_PIO_OUT_PIXEL_RATE_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:a93050e6b1ea95d7147823e81113e6919"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Rate Shift.  <a href="#a93050e6b1ea95d7147823e81113e6919">More...</a><br/></td></tr>
<tr class="separator:a93050e6b1ea95d7147823e81113e6919"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab7a79de3656d1b5fcaf1143c9a8ddd4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab7a79de3656d1b5fcaf1143c9a8ddd4d">XV_HDMIRX_PIO_OUT_SAMPLE_RATE_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ab7a79de3656d1b5fcaf1143c9a8ddd4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Sample Rate shift.  <a href="#ab7a79de3656d1b5fcaf1143c9a8ddd4d">More...</a><br/></td></tr>
<tr class="separator:ab7a79de3656d1b5fcaf1143c9a8ddd4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5c1716813413cd8ca952fafe0520b782"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a5c1716813413cd8ca952fafe0520b782">XV_HDMIRX_PIO_OUT_COLOR_SPACE_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:a5c1716813413cd8ca952fafe0520b782"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Space shift.  <a href="#a5c1716813413cd8ca952fafe0520b782">More...</a><br/></td></tr>
<tr class="separator:a5c1716813413cd8ca952fafe0520b782"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a923b78bca6113c26d4c9aa2450e12d31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a923b78bca6113c26d4c9aa2450e12d31">XV_HDMIRX_PIO_OUT_SCRM_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:a923b78bca6113c26d4c9aa2450e12d31"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Scrambler mask.  <a href="#a923b78bca6113c26d4c9aa2450e12d31">More...</a><br/></td></tr>
<tr class="separator:a923b78bca6113c26d4c9aa2450e12d31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade6f035d0bef0ec35894c6d90d700f16"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ade6f035d0bef0ec35894c6d90d700f16">XV_HDMIRX_PIO_OUT_BRIDGE_YUV420_MASK</a>&#160;&#160;&#160;(1&lt;&lt;29)</td></tr>
<tr class="memdesc:ade6f035d0bef0ec35894c6d90d700f16"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Bridge_YUV420 mask.  <a href="#ade6f035d0bef0ec35894c6d90d700f16">More...</a><br/></td></tr>
<tr class="separator:ade6f035d0bef0ec35894c6d90d700f16"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a818e2b5f24ae64c160d8291e2a72bbb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a818e2b5f24ae64c160d8291e2a72bbb3">XV_HDMIRX_PIO_OUT_BRIDGE_PIXEL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;30)</td></tr>
<tr class="memdesc:a818e2b5f24ae64c160d8291e2a72bbb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Bridge_Pixel drop mask.  <a href="#a818e2b5f24ae64c160d8291e2a72bbb3">More...</a><br/></td></tr>
<tr class="separator:a818e2b5f24ae64c160d8291e2a72bbb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a122cccfebb05738c47f29c3880fdafee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a122cccfebb05738c47f29c3880fdafee">XV_HDMIRX_PIO_OUT_INT_VRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a122cccfebb05738c47f29c3880fdafee"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out INT_VRST mask.  <a href="#a122cccfebb05738c47f29c3880fdafee">More...</a><br/></td></tr>
<tr class="separator:a122cccfebb05738c47f29c3880fdafee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a218ac4dfa25332f50ef814896cbc645a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a218ac4dfa25332f50ef814896cbc645a">XV_HDMIRX_PIO_OUT_INT_LRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;20)</td></tr>
<tr class="memdesc:a218ac4dfa25332f50ef814896cbc645a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out INT_LRST mask.  <a href="#a218ac4dfa25332f50ef814896cbc645a">More...</a><br/></td></tr>
<tr class="separator:a218ac4dfa25332f50ef814896cbc645a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a44d92cc10a5825726f4ab69f1fef3039"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a44d92cc10a5825726f4ab69f1fef3039">XV_HDMIRX_PIO_OUT_EXT_VRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;21)</td></tr>
<tr class="memdesc:a44d92cc10a5825726f4ab69f1fef3039"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out EXT_VRST mask.  <a href="#a44d92cc10a5825726f4ab69f1fef3039">More...</a><br/></td></tr>
<tr class="separator:a44d92cc10a5825726f4ab69f1fef3039"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a67a9be2365d43364996b89791e0f45aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a67a9be2365d43364996b89791e0f45aa">XV_HDMIRX_PIO_OUT_EXT_SYSRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;22)</td></tr>
<tr class="memdesc:a67a9be2365d43364996b89791e0f45aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out EXT_SYSRST mask.  <a href="#a67a9be2365d43364996b89791e0f45aa">More...</a><br/></td></tr>
<tr class="separator:a67a9be2365d43364996b89791e0f45aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aac130c5fe1e9b758f5461b5ef6cd6d22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aac130c5fe1e9b758f5461b5ef6cd6d22">XV_HDMIRX_PIO_IN_DET_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aac130c5fe1e9b758f5461b5ef6cd6d22"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In cable detect mask.  <a href="#aac130c5fe1e9b758f5461b5ef6cd6d22">More...</a><br/></td></tr>
<tr class="separator:aac130c5fe1e9b758f5461b5ef6cd6d22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7f6d5c17336a530b92869fa191b8cc8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a7f6d5c17336a530b92869fa191b8cc8f">XV_HDMIRX_PIO_IN_LNK_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a7f6d5c17336a530b92869fa191b8cc8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In link ready mask.  <a href="#a7f6d5c17336a530b92869fa191b8cc8f">More...</a><br/></td></tr>
<tr class="separator:a7f6d5c17336a530b92869fa191b8cc8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a477171cef5c2a0b4621facbb41b82eb8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a477171cef5c2a0b4621facbb41b82eb8">XV_HDMIRX_PIO_IN_VID_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a477171cef5c2a0b4621facbb41b82eb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In video ready mask.  <a href="#a477171cef5c2a0b4621facbb41b82eb8">More...</a><br/></td></tr>
<tr class="separator:a477171cef5c2a0b4621facbb41b82eb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af32e3df9ebde480b8a20e03ec37a03eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af32e3df9ebde480b8a20e03ec37a03eb">XV_HDMIRX_PIO_IN_MODE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:af32e3df9ebde480b8a20e03ec37a03eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Mode mask.  <a href="#af32e3df9ebde480b8a20e03ec37a03eb">More...</a><br/></td></tr>
<tr class="separator:af32e3df9ebde480b8a20e03ec37a03eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a257587f5ad87dd0795d3891d3fda3ac6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a257587f5ad87dd0795d3891d3fda3ac6">XV_HDMIRX_PIO_IN_SCRAMBLER_LOCK0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a257587f5ad87dd0795d3891d3fda3ac6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Scrambler lock 0 mask.  <a href="#a257587f5ad87dd0795d3891d3fda3ac6">More...</a><br/></td></tr>
<tr class="separator:a257587f5ad87dd0795d3891d3fda3ac6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abf5edbd5735e21545ab367940bb59aa3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#abf5edbd5735e21545ab367940bb59aa3">XV_HDMIRX_PIO_IN_SCRAMBLER_LOCK1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:abf5edbd5735e21545ab367940bb59aa3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Scrambler lock 1 mask.  <a href="#abf5edbd5735e21545ab367940bb59aa3">More...</a><br/></td></tr>
<tr class="separator:abf5edbd5735e21545ab367940bb59aa3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a28904b530f07081146e224cc033c3cdb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a28904b530f07081146e224cc033c3cdb">XV_HDMIRX_PIO_IN_SCRAMBLER_LOCK2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:a28904b530f07081146e224cc033c3cdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Scrambler lock 2 mask.  <a href="#a28904b530f07081146e224cc033c3cdb">More...</a><br/></td></tr>
<tr class="separator:a28904b530f07081146e224cc033c3cdb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a63a6b5dcd3cd49bbc464bc67f3ad36cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a63a6b5dcd3cd49bbc464bc67f3ad36cf">XV_HDMIRX_PIO_IN_SCDC_SCRAMBLER_ENABLE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:a63a6b5dcd3cd49bbc464bc67f3ad36cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In SCDC scrambler enable mask.  <a href="#a63a6b5dcd3cd49bbc464bc67f3ad36cf">More...</a><br/></td></tr>
<tr class="separator:a63a6b5dcd3cd49bbc464bc67f3ad36cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af439412374d6713f5b5a375c54d9df68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af439412374d6713f5b5a375c54d9df68">XV_HDMIRX_PIO_IN_SCDC_TMDS_CLOCK_RATIO_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:af439412374d6713f5b5a375c54d9df68"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In SCDC TMDS clock ratio mask.  <a href="#af439412374d6713f5b5a375c54d9df68">More...</a><br/></td></tr>
<tr class="separator:af439412374d6713f5b5a375c54d9df68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acd03df9d68c4ed7f25d23ee69306f407"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#acd03df9d68c4ed7f25d23ee69306f407">XV_HDMIRX_PIO_IN_ALIGNER_LOCK_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:acd03df9d68c4ed7f25d23ee69306f407"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In alinger lock mask.  <a href="#acd03df9d68c4ed7f25d23ee69306f407">More...</a><br/></td></tr>
<tr class="separator:acd03df9d68c4ed7f25d23ee69306f407"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0b106779d6898b53b151f107745c119"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aa0b106779d6898b53b151f107745c119">XV_HDMIRX_PIO_IN_BRDG_OVERFLOW_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:aa0b106779d6898b53b151f107745c119"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In bridge overflow mask.  <a href="#aa0b106779d6898b53b151f107745c119">More...</a><br/></td></tr>
<tr class="separator:aa0b106779d6898b53b151f107745c119"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0cf543f243de78f481f48c4639ac1f94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a0cf543f243de78f481f48c4639ac1f94">XV_HDMIRX_TMR_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(0*4))</td></tr>
<tr class="memdesc:a0cf543f243de78f481f48c4639ac1f94"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Identification register offset.  <a href="#a0cf543f243de78f481f48c4639ac1f94">More...</a><br/></td></tr>
<tr class="separator:a0cf543f243de78f481f48c4639ac1f94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadd3b41587950a820be6cdacc340bef3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aadd3b41587950a820be6cdacc340bef3">XV_HDMIRX_TMR_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(1*4))</td></tr>
<tr class="memdesc:aadd3b41587950a820be6cdacc340bef3"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control register offset.  <a href="#aadd3b41587950a820be6cdacc340bef3">More...</a><br/></td></tr>
<tr class="separator:aadd3b41587950a820be6cdacc340bef3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acfb602db80f1b5565752761a4e1d3203"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#acfb602db80f1b5565752761a4e1d3203">XV_HDMIRX_TMR_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(2*4))</td></tr>
<tr class="memdesc:acfb602db80f1b5565752761a4e1d3203"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Register Set offset.  <a href="#acfb602db80f1b5565752761a4e1d3203">More...</a><br/></td></tr>
<tr class="separator:acfb602db80f1b5565752761a4e1d3203"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a418a4e82c61dfecb6fba2ae6fa645cc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a418a4e82c61dfecb6fba2ae6fa645cc5">XV_HDMIRX_TMR_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(3*4))</td></tr>
<tr class="memdesc:a418a4e82c61dfecb6fba2ae6fa645cc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Register Clear offset.  <a href="#a418a4e82c61dfecb6fba2ae6fa645cc5">More...</a><br/></td></tr>
<tr class="separator:a418a4e82c61dfecb6fba2ae6fa645cc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a2a11c35b8b89348b193ce2273b0044"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a8a2a11c35b8b89348b193ce2273b0044">XV_HDMIRX_TMR_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(4*4))</td></tr>
<tr class="memdesc:a8a2a11c35b8b89348b193ce2273b0044"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Status Register offset.  <a href="#a8a2a11c35b8b89348b193ce2273b0044">More...</a><br/></td></tr>
<tr class="separator:a8a2a11c35b8b89348b193ce2273b0044"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acc84ec76d1d4480d32bfcc0a6d36c9cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#acc84ec76d1d4480d32bfcc0a6d36c9cf">XV_HDMIRX_TMR_CNT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(5*4))</td></tr>
<tr class="memdesc:acc84ec76d1d4480d32bfcc0a6d36c9cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Counter Register offset.  <a href="#acc84ec76d1d4480d32bfcc0a6d36c9cf">More...</a><br/></td></tr>
<tr class="separator:acc84ec76d1d4480d32bfcc0a6d36c9cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1583ebb7279d885effb9fcdd993210fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a1583ebb7279d885effb9fcdd993210fd">XV_HDMIRX_TMR_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a1583ebb7279d885effb9fcdd993210fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Run mask.  <a href="#a1583ebb7279d885effb9fcdd993210fd">More...</a><br/></td></tr>
<tr class="separator:a1583ebb7279d885effb9fcdd993210fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a32d7a633d71248f00c6c3a0c4cc45709"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a32d7a633d71248f00c6c3a0c4cc45709">XV_HDMIRX_TMR_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a32d7a633d71248f00c6c3a0c4cc45709"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Interrupt Enable mask.  <a href="#a32d7a633d71248f00c6c3a0c4cc45709">More...</a><br/></td></tr>
<tr class="separator:a32d7a633d71248f00c6c3a0c4cc45709"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa15bfe16e6a4aa77cc680ea22cd03c9c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aa15bfe16e6a4aa77cc680ea22cd03c9c">XV_HDMIRX_TMR_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aa15bfe16e6a4aa77cc680ea22cd03c9c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Status Interrupt mask.  <a href="#aa15bfe16e6a4aa77cc680ea22cd03c9c">More...</a><br/></td></tr>
<tr class="separator:aa15bfe16e6a4aa77cc680ea22cd03c9c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8561f573c1afd06984ecd2fc0c3ffd3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a8561f573c1afd06984ecd2fc0c3ffd3b">XV_HDMIRX_TMR_STA_CNT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a8561f573c1afd06984ecd2fc0c3ffd3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Status counter Event mask.  <a href="#a8561f573c1afd06984ecd2fc0c3ffd3b">More...</a><br/></td></tr>
<tr class="separator:a8561f573c1afd06984ecd2fc0c3ffd3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1962a0c3c80aa477e98f25e99aeae0d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a1962a0c3c80aa477e98f25e99aeae0d7">XV_HDMIRX_VTD_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(0*4))</td></tr>
<tr class="memdesc:a1962a0c3c80aa477e98f25e99aeae0d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Identification Register offset.  <a href="#a1962a0c3c80aa477e98f25e99aeae0d7">More...</a><br/></td></tr>
<tr class="separator:a1962a0c3c80aa477e98f25e99aeae0d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acc56d3a8152c535ce8783d2ff82f4227"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#acc56d3a8152c535ce8783d2ff82f4227">XV_HDMIRX_VTD_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(1*4))</td></tr>
<tr class="memdesc:acc56d3a8152c535ce8783d2ff82f4227"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Register offset.  <a href="#acc56d3a8152c535ce8783d2ff82f4227">More...</a><br/></td></tr>
<tr class="separator:acc56d3a8152c535ce8783d2ff82f4227"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af82aee3a907bcd6e34308267e8d67014"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af82aee3a907bcd6e34308267e8d67014">XV_HDMIRX_VTD_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(2*4))</td></tr>
<tr class="memdesc:af82aee3a907bcd6e34308267e8d67014"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Set Register offset.  <a href="#af82aee3a907bcd6e34308267e8d67014">More...</a><br/></td></tr>
<tr class="separator:af82aee3a907bcd6e34308267e8d67014"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acbbb7da3f11adf6adaeb53543411f7b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#acbbb7da3f11adf6adaeb53543411f7b2">XV_HDMIRX_VTD_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(3*4))</td></tr>
<tr class="memdesc:acbbb7da3f11adf6adaeb53543411f7b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Clear Register offset.  <a href="#acbbb7da3f11adf6adaeb53543411f7b2">More...</a><br/></td></tr>
<tr class="separator:acbbb7da3f11adf6adaeb53543411f7b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0927784dd0514805715557437733268"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aa0927784dd0514805715557437733268">XV_HDMIRX_VTD_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(4*4))</td></tr>
<tr class="memdesc:aa0927784dd0514805715557437733268"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Register offset.  <a href="#aa0927784dd0514805715557437733268">More...</a><br/></td></tr>
<tr class="separator:aa0927784dd0514805715557437733268"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada7dd9b96b61f5400488120a035a733c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ada7dd9b96b61f5400488120a035a733c">XV_HDMIRX_VTD_TOT_PIX_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(5*4))</td></tr>
<tr class="memdesc:ada7dd9b96b61f5400488120a035a733c"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Total Pixels Register offset.  <a href="#ada7dd9b96b61f5400488120a035a733c">More...</a><br/></td></tr>
<tr class="separator:ada7dd9b96b61f5400488120a035a733c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a680b488ede6d6a8ec9d730deff7559e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a680b488ede6d6a8ec9d730deff7559e8">XV_HDMIRX_VTD_ACT_PIX_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(6*4))</td></tr>
<tr class="memdesc:a680b488ede6d6a8ec9d730deff7559e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Active Pixels Register offset.  <a href="#a680b488ede6d6a8ec9d730deff7559e8">More...</a><br/></td></tr>
<tr class="separator:a680b488ede6d6a8ec9d730deff7559e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a760c24aa9d33dd2727c6106537c4723d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a760c24aa9d33dd2727c6106537c4723d">XV_HDMIRX_VTD_TOT_LIN_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(7*4))</td></tr>
<tr class="memdesc:a760c24aa9d33dd2727c6106537c4723d"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Total Lines Register offset.  <a href="#a760c24aa9d33dd2727c6106537c4723d">More...</a><br/></td></tr>
<tr class="separator:a760c24aa9d33dd2727c6106537c4723d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8e1330cc6542ff96733cb7f7e29465fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a8e1330cc6542ff96733cb7f7e29465fc">XV_HDMIRX_VTD_ACT_LIN_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(8*4))</td></tr>
<tr class="memdesc:a8e1330cc6542ff96733cb7f7e29465fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Active Lines Register offset.  <a href="#a8e1330cc6542ff96733cb7f7e29465fc">More...</a><br/></td></tr>
<tr class="separator:a8e1330cc6542ff96733cb7f7e29465fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a38aa5d3cc486342d8414cccece29d578"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a38aa5d3cc486342d8414cccece29d578">XV_HDMIRX_VTD_VSW_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(9*4))</td></tr>
<tr class="memdesc:a38aa5d3cc486342d8414cccece29d578"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Vertical Sync Width Register offset.  <a href="#a38aa5d3cc486342d8414cccece29d578">More...</a><br/></td></tr>
<tr class="separator:a38aa5d3cc486342d8414cccece29d578"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a18b3fcc81e0b4ebffe5d03b93b9e3a92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a18b3fcc81e0b4ebffe5d03b93b9e3a92">XV_HDMIRX_VTD_HSW_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(10*4))</td></tr>
<tr class="memdesc:a18b3fcc81e0b4ebffe5d03b93b9e3a92"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Horizontal Sync Width Register offset.  <a href="#a18b3fcc81e0b4ebffe5d03b93b9e3a92">More...</a><br/></td></tr>
<tr class="separator:a18b3fcc81e0b4ebffe5d03b93b9e3a92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7976bef95da52ceaf075d949bbf95fe4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a7976bef95da52ceaf075d949bbf95fe4">XV_HDMIRX_VTD_VFP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(11*4))</td></tr>
<tr class="memdesc:a7976bef95da52ceaf075d949bbf95fe4"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Vertical Front Porch Register offset.  <a href="#a7976bef95da52ceaf075d949bbf95fe4">More...</a><br/></td></tr>
<tr class="separator:a7976bef95da52ceaf075d949bbf95fe4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f25a70ae387411851a4e26d62c4a42a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a0f25a70ae387411851a4e26d62c4a42a">XV_HDMIRX_VTD_VBP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(12*4))</td></tr>
<tr class="memdesc:a0f25a70ae387411851a4e26d62c4a42a"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Vertical Back Porch Register offset.  <a href="#a0f25a70ae387411851a4e26d62c4a42a">More...</a><br/></td></tr>
<tr class="separator:a0f25a70ae387411851a4e26d62c4a42a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d1c2a6712699269f8e69dd2c576a3eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a9d1c2a6712699269f8e69dd2c576a3eb">XV_HDMIRX_VTD_HFP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(13*4))</td></tr>
<tr class="memdesc:a9d1c2a6712699269f8e69dd2c576a3eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Horizontal Front Porch Register offset.  <a href="#a9d1c2a6712699269f8e69dd2c576a3eb">More...</a><br/></td></tr>
<tr class="separator:a9d1c2a6712699269f8e69dd2c576a3eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae639e59a8ebf41da214a1de1246feae3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ae639e59a8ebf41da214a1de1246feae3">XV_HDMIRX_VTD_HBP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(14*4))</td></tr>
<tr class="memdesc:ae639e59a8ebf41da214a1de1246feae3"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Horizontal Back Porch Register offset.  <a href="#ae639e59a8ebf41da214a1de1246feae3">More...</a><br/></td></tr>
<tr class="separator:ae639e59a8ebf41da214a1de1246feae3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af9e3cef6d874c106289bb83133776baf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af9e3cef6d874c106289bb83133776baf">XV_HDMIRX_VTD_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:af9e3cef6d874c106289bb83133776baf"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Run mask.  <a href="#af9e3cef6d874c106289bb83133776baf">More...</a><br/></td></tr>
<tr class="separator:af9e3cef6d874c106289bb83133776baf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a742400164fe40d8d72d309affc8d2bf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a742400164fe40d8d72d309affc8d2bf2">XV_HDMIRX_VTD_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a742400164fe40d8d72d309affc8d2bf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Interrupt Enable mask.  <a href="#a742400164fe40d8d72d309affc8d2bf2">More...</a><br/></td></tr>
<tr class="separator:a742400164fe40d8d72d309affc8d2bf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a79e70fa96e30594b7f96286c786a8ab6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a79e70fa96e30594b7f96286c786a8ab6">XV_HDMIRX_VTD_CTRL_FIELD_POL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a79e70fa96e30594b7f96286c786a8ab6"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control field polarity mask.  <a href="#a79e70fa96e30594b7f96286c786a8ab6">More...</a><br/></td></tr>
<tr class="separator:a79e70fa96e30594b7f96286c786a8ab6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52ae42852070a50b3a7229c2f66462bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a52ae42852070a50b3a7229c2f66462bd">XV_HDMIRX_VTD_CTRL_SYNC_LOSS_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a52ae42852070a50b3a7229c2f66462bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control field polarity mask.  <a href="#a52ae42852070a50b3a7229c2f66462bd">More...</a><br/></td></tr>
<tr class="separator:a52ae42852070a50b3a7229c2f66462bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab645b5a6852d39b83d669dd90fb5d383"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab645b5a6852d39b83d669dd90fb5d383">XV_HDMIRX_VTD_CTRL_TIMEBASE_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ab645b5a6852d39b83d669dd90fb5d383"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control timebase shift.  <a href="#ab645b5a6852d39b83d669dd90fb5d383">More...</a><br/></td></tr>
<tr class="separator:ab645b5a6852d39b83d669dd90fb5d383"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a829444947a7549a148b9f77c162def4f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a829444947a7549a148b9f77c162def4f">XV_HDMIRX_VTD_CTRL_TIMERBASE_MASK</a>&#160;&#160;&#160;0xffffff</td></tr>
<tr class="memdesc:a829444947a7549a148b9f77c162def4f"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control timebase mask.  <a href="#a829444947a7549a148b9f77c162def4f">More...</a><br/></td></tr>
<tr class="separator:a829444947a7549a148b9f77c162def4f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeb5ef898fca55fa90ee72374af67f0ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aeb5ef898fca55fa90ee72374af67f0ae">XV_HDMIRX_VTD_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aeb5ef898fca55fa90ee72374af67f0ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Interrupt mask.  <a href="#aeb5ef898fca55fa90ee72374af67f0ae">More...</a><br/></td></tr>
<tr class="separator:aeb5ef898fca55fa90ee72374af67f0ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1f2b2eef2e119965b72bc6ba2d631cb8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a1f2b2eef2e119965b72bc6ba2d631cb8">XV_HDMIRX_VTD_STA_TIMEBASE_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a1f2b2eef2e119965b72bc6ba2d631cb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status timebase event mask.  <a href="#a1f2b2eef2e119965b72bc6ba2d631cb8">More...</a><br/></td></tr>
<tr class="separator:a1f2b2eef2e119965b72bc6ba2d631cb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa003ad3deba710d8250e4d09c3d706a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aa003ad3deba710d8250e4d09c3d706a4">XV_HDMIRX_VTD_STA_VS_POL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:aa003ad3deba710d8250e4d09c3d706a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Vsync Polarity mask.  <a href="#aa003ad3deba710d8250e4d09c3d706a4">More...</a><br/></td></tr>
<tr class="separator:aa003ad3deba710d8250e4d09c3d706a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abb3320c46658b4aaa9faa3c78f535fd1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#abb3320c46658b4aaa9faa3c78f535fd1">XV_HDMIRX_VTD_STA_HS_POL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:abb3320c46658b4aaa9faa3c78f535fd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Hsync Polarity mask.  <a href="#abb3320c46658b4aaa9faa3c78f535fd1">More...</a><br/></td></tr>
<tr class="separator:abb3320c46658b4aaa9faa3c78f535fd1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8810fe79655104c0b273b6868b2407fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a8810fe79655104c0b273b6868b2407fb">XV_HDMIRX_VTD_STA_FMT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:a8810fe79655104c0b273b6868b2407fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Format mask.  <a href="#a8810fe79655104c0b273b6868b2407fb">More...</a><br/></td></tr>
<tr class="separator:a8810fe79655104c0b273b6868b2407fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae3bf1496b2a02b5d4403d08676ae052e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ae3bf1496b2a02b5d4403d08676ae052e">XV_HDMIRX_VTD_STA_SYNC_LOSS_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:ae3bf1496b2a02b5d4403d08676ae052e"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Sync Loss mask.  <a href="#ae3bf1496b2a02b5d4403d08676ae052e">More...</a><br/></td></tr>
<tr class="separator:ae3bf1496b2a02b5d4403d08676ae052e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad73e990f64f6dd2501e19b8ec873f26a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ad73e990f64f6dd2501e19b8ec873f26a">XV_HDMIRX_DDC_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(0*4))</td></tr>
<tr class="memdesc:ad73e990f64f6dd2501e19b8ec873f26a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Identification Register offset.  <a href="#ad73e990f64f6dd2501e19b8ec873f26a">More...</a><br/></td></tr>
<tr class="separator:ad73e990f64f6dd2501e19b8ec873f26a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a103df1d10146f4676b28638b418bca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a7a103df1d10146f4676b28638b418bca">XV_HDMIRX_DDC_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(1*4))</td></tr>
<tr class="memdesc:a7a103df1d10146f4676b28638b418bca"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register offset.  <a href="#a7a103df1d10146f4676b28638b418bca">More...</a><br/></td></tr>
<tr class="separator:a7a103df1d10146f4676b28638b418bca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8272d8237c5560511743f6645351c889"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a8272d8237c5560511743f6645351c889">XV_HDMIRX_DDC_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(2*4))</td></tr>
<tr class="memdesc:a8272d8237c5560511743f6645351c889"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register Set offset.  <a href="#a8272d8237c5560511743f6645351c889">More...</a><br/></td></tr>
<tr class="separator:a8272d8237c5560511743f6645351c889"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac5fcd5ad68b451baf56e90de899e7ede"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ac5fcd5ad68b451baf56e90de899e7ede">XV_HDMIRX_DDC_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(3*4))</td></tr>
<tr class="memdesc:ac5fcd5ad68b451baf56e90de899e7ede"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register Clear offset.  <a href="#ac5fcd5ad68b451baf56e90de899e7ede">More...</a><br/></td></tr>
<tr class="separator:ac5fcd5ad68b451baf56e90de899e7ede"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2549440290b1505f595c0986c5fe6f13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a2549440290b1505f595c0986c5fe6f13">XV_HDMIRX_DDC_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(4*4))</td></tr>
<tr class="memdesc:a2549440290b1505f595c0986c5fe6f13"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Register offset.  <a href="#a2549440290b1505f595c0986c5fe6f13">More...</a><br/></td></tr>
<tr class="separator:a2549440290b1505f595c0986c5fe6f13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a353a7e74a37ccc5fe06e7dfbf1d1e05d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a353a7e74a37ccc5fe06e7dfbf1d1e05d">XV_HDMIRX_DDC_EDID_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(5*4))</td></tr>
<tr class="memdesc:a353a7e74a37ccc5fe06e7dfbf1d1e05d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC EDID Status Register offset.  <a href="#a353a7e74a37ccc5fe06e7dfbf1d1e05d">More...</a><br/></td></tr>
<tr class="separator:a353a7e74a37ccc5fe06e7dfbf1d1e05d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af496088efcd5b696f2c6a53b19c73679"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af496088efcd5b696f2c6a53b19c73679">XV_HDMIRX_DDC_HDCP_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(6*4))</td></tr>
<tr class="memdesc:af496088efcd5b696f2c6a53b19c73679"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC HDCP Status Register offset.  <a href="#af496088efcd5b696f2c6a53b19c73679">More...</a><br/></td></tr>
<tr class="separator:af496088efcd5b696f2c6a53b19c73679"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a659ddc496ff647b94aab4c2e401eb131"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a659ddc496ff647b94aab4c2e401eb131">XV_HDMIRX_DDC_EDID_SP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(8*4))</td></tr>
<tr class="memdesc:a659ddc496ff647b94aab4c2e401eb131"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read EDID segment pointer offset.  <a href="#a659ddc496ff647b94aab4c2e401eb131">More...</a><br/></td></tr>
<tr class="separator:a659ddc496ff647b94aab4c2e401eb131"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd5e2bee6eb83de864de63600afef44d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#abd5e2bee6eb83de864de63600afef44d">XV_HDMIRX_DDC_EDID_WP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(9*4))</td></tr>
<tr class="memdesc:abd5e2bee6eb83de864de63600afef44d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read EDID write pointer offset.  <a href="#abd5e2bee6eb83de864de63600afef44d">More...</a><br/></td></tr>
<tr class="separator:abd5e2bee6eb83de864de63600afef44d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8b682b85fe84e6b981cd441bc1e737c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a8b682b85fe84e6b981cd441bc1e737c1">XV_HDMIRX_DDC_EDID_RP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(10*4))</td></tr>
<tr class="memdesc:a8b682b85fe84e6b981cd441bc1e737c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read EDID read pointer offset.  <a href="#a8b682b85fe84e6b981cd441bc1e737c1">More...</a><br/></td></tr>
<tr class="separator:a8b682b85fe84e6b981cd441bc1e737c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a87d82ea13dd71da7ed87b4645b056dd5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a87d82ea13dd71da7ed87b4645b056dd5">XV_HDMIRX_DDC_EDID_DATA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(11*4))</td></tr>
<tr class="memdesc:a87d82ea13dd71da7ed87b4645b056dd5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read EDID data offset.  <a href="#a87d82ea13dd71da7ed87b4645b056dd5">More...</a><br/></td></tr>
<tr class="separator:a87d82ea13dd71da7ed87b4645b056dd5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6b100412180e030ef95cb8ecaa5934b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a6b100412180e030ef95cb8ecaa5934b3">XV_HDMIRX_DDC_HDCP_ADDRESS_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(12*4))</td></tr>
<tr class="memdesc:a6b100412180e030ef95cb8ecaa5934b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read HDCP address offset.  <a href="#a6b100412180e030ef95cb8ecaa5934b3">More...</a><br/></td></tr>
<tr class="separator:a6b100412180e030ef95cb8ecaa5934b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acc2e9a9d6af18df813b60237a319900a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#acc2e9a9d6af18df813b60237a319900a">XV_HDMIRX_DDC_HDCP_DATA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(13*4))</td></tr>
<tr class="memdesc:acc2e9a9d6af18df813b60237a319900a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read HDCP data offset.  <a href="#acc2e9a9d6af18df813b60237a319900a">More...</a><br/></td></tr>
<tr class="separator:acc2e9a9d6af18df813b60237a319900a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91f5315d7efd6486cef6ed81161c1411"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a91f5315d7efd6486cef6ed81161c1411">XV_HDMIRX_DDC_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a91f5315d7efd6486cef6ed81161c1411"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Run mask.  <a href="#a91f5315d7efd6486cef6ed81161c1411">More...</a><br/></td></tr>
<tr class="separator:a91f5315d7efd6486cef6ed81161c1411"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acda38629aa70cc313c59ba64eb8e3318"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#acda38629aa70cc313c59ba64eb8e3318">XV_HDMIRX_DDC_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:acda38629aa70cc313c59ba64eb8e3318"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Interrupt enable mask.  <a href="#acda38629aa70cc313c59ba64eb8e3318">More...</a><br/></td></tr>
<tr class="separator:acda38629aa70cc313c59ba64eb8e3318"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a92855dc688a9f79d080f1eab92e17144"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a92855dc688a9f79d080f1eab92e17144">XV_HDMIRX_DDC_CTRL_EDID_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a92855dc688a9f79d080f1eab92e17144"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control EDID enable mask.  <a href="#a92855dc688a9f79d080f1eab92e17144">More...</a><br/></td></tr>
<tr class="separator:a92855dc688a9f79d080f1eab92e17144"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a70913fe092b1adef31afb152cd679de3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a70913fe092b1adef31afb152cd679de3">XV_HDMIRX_DDC_CTRL_SCDC_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a70913fe092b1adef31afb152cd679de3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control SCDC enable mask.  <a href="#a70913fe092b1adef31afb152cd679de3">More...</a><br/></td></tr>
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<tr class="memitem:a937baab4a62131f510e87602c5e5f669"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a937baab4a62131f510e87602c5e5f669">XV_HDMIRX_DDC_CTRL_HDCP_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a937baab4a62131f510e87602c5e5f669"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control HDCP enable mask.  <a href="#a937baab4a62131f510e87602c5e5f669">More...</a><br/></td></tr>
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<tr class="memitem:a2fcc95a6129eacc331e014e496db9031"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a2fcc95a6129eacc331e014e496db9031">XV_HDMIRX_DDC_CTRL_SCDC_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:a2fcc95a6129eacc331e014e496db9031"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control SCDC clear mask.  <a href="#a2fcc95a6129eacc331e014e496db9031">More...</a><br/></td></tr>
<tr class="separator:a2fcc95a6129eacc331e014e496db9031"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0210e2d1fa6287ae916903a548246052"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a0210e2d1fa6287ae916903a548246052">XV_HDMIRX_DDC_CTRL_WMSG_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:a0210e2d1fa6287ae916903a548246052"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control write message clear mask.  <a href="#a0210e2d1fa6287ae916903a548246052">More...</a><br/></td></tr>
<tr class="separator:a0210e2d1fa6287ae916903a548246052"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af8e7afbf29117f39c72339d26872246a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af8e7afbf29117f39c72339d26872246a">XV_HDMIRX_DDC_CTRL_RMSG_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:af8e7afbf29117f39c72339d26872246a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control read message clear mask.  <a href="#af8e7afbf29117f39c72339d26872246a">More...</a><br/></td></tr>
<tr class="separator:af8e7afbf29117f39c72339d26872246a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab8ef6708fce427ed656a9a7c2c0f8e63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab8ef6708fce427ed656a9a7c2c0f8e63">XV_HDMIRX_DDC_CTRL_HDCP_MODE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:ab8ef6708fce427ed656a9a7c2c0f8e63"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control HDCP mode mask.  <a href="#ab8ef6708fce427ed656a9a7c2c0f8e63">More...</a><br/></td></tr>
<tr class="separator:ab8ef6708fce427ed656a9a7c2c0f8e63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeacfe034e74301f0f50846e09966266f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aeacfe034e74301f0f50846e09966266f">XV_HDMIRX_DDC_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aeacfe034e74301f0f50846e09966266f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Interrupt mask.  <a href="#aeacfe034e74301f0f50846e09966266f">More...</a><br/></td></tr>
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<tr class="memitem:a6ea0539a870ea8cf811427f6161820aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a6ea0539a870ea8cf811427f6161820aa">XV_HDMIRX_DDC_STA_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a6ea0539a870ea8cf811427f6161820aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Event mask.  <a href="#a6ea0539a870ea8cf811427f6161820aa">More...</a><br/></td></tr>
<tr class="separator:a6ea0539a870ea8cf811427f6161820aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeb8c90015c1fe7b50a3c5707aad8c259"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aeb8c90015c1fe7b50a3c5707aad8c259">XV_HDMIRX_DDC_STA_BUSY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:aeb8c90015c1fe7b50a3c5707aad8c259"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Busy mask.  <a href="#aeb8c90015c1fe7b50a3c5707aad8c259">More...</a><br/></td></tr>
<tr class="separator:aeb8c90015c1fe7b50a3c5707aad8c259"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a343d84b77859271fd326e2e8e8050fcd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a343d84b77859271fd326e2e8e8050fcd">XV_HDMIRX_DDC_STA_SCL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a343d84b77859271fd326e2e8e8050fcd"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status state of the SCL input mask.  <a href="#a343d84b77859271fd326e2e8e8050fcd">More...</a><br/></td></tr>
<tr class="separator:a343d84b77859271fd326e2e8e8050fcd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af2cb844892744258e47f631cc8f1ef59"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af2cb844892744258e47f631cc8f1ef59">XV_HDMIRX_DDC_STA_SDA_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:af2cb844892744258e47f631cc8f1ef59"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status state of the SDA input mask.  <a href="#af2cb844892744258e47f631cc8f1ef59">More...</a><br/></td></tr>
<tr class="separator:af2cb844892744258e47f631cc8f1ef59"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af0335ac9bfb482b90c413e7e7d4d65e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af0335ac9bfb482b90c413e7e7d4d65e8">XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:af0335ac9bfb482b90c413e7e7d4d65e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP AKSV event mask.  <a href="#af0335ac9bfb482b90c413e7e7d4d65e8">More...</a><br/></td></tr>
<tr class="separator:af0335ac9bfb482b90c413e7e7d4d65e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a252423ec30ee3265d9a030570410bb31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a252423ec30ee3265d9a030570410bb31">XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:a252423ec30ee3265d9a030570410bb31"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP write message buffer new event mask.  <a href="#a252423ec30ee3265d9a030570410bb31">More...</a><br/></td></tr>
<tr class="separator:a252423ec30ee3265d9a030570410bb31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a05164fc716abd92dac3e68f6c3155dba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a05164fc716abd92dac3e68f6c3155dba">XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:a05164fc716abd92dac3e68f6c3155dba"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP read message buffer end event mask.  <a href="#a05164fc716abd92dac3e68f6c3155dba">More...</a><br/></td></tr>
<tr class="separator:a05164fc716abd92dac3e68f6c3155dba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af1dae57555c3bf8b0ae6e23ec0246335"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af1dae57555c3bf8b0ae6e23ec0246335">XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:af1dae57555c3bf8b0ae6e23ec0246335"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP read message buffer not completed event mask.  <a href="#af1dae57555c3bf8b0ae6e23ec0246335">More...</a><br/></td></tr>
<tr class="separator:af1dae57555c3bf8b0ae6e23ec0246335"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac3a39ab59bd30321754bf64a2c69bfca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ac3a39ab59bd30321754bf64a2c69bfca">XV_HDMIRX_DDC_STA_HDCP_1_PROT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:ac3a39ab59bd30321754bf64a2c69bfca"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 1.4 protocol flag.  <a href="#ac3a39ab59bd30321754bf64a2c69bfca">More...</a><br/></td></tr>
<tr class="separator:ac3a39ab59bd30321754bf64a2c69bfca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b4f8b5dd134ed31ef8e417d18f75ecf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a0b4f8b5dd134ed31ef8e417d18f75ecf">XV_HDMIRX_DDC_STA_HDCP_2_PROT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:a0b4f8b5dd134ed31ef8e417d18f75ecf"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 protocol flag.  <a href="#a0b4f8b5dd134ed31ef8e417d18f75ecf">More...</a><br/></td></tr>
<tr class="separator:a0b4f8b5dd134ed31ef8e417d18f75ecf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad721a69e5af00f6de0a549db2c785385"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ad721a69e5af00f6de0a549db2c785385">XV_HDMIRX_DDC_STA_HDCP_1_PROT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;11)</td></tr>
<tr class="memdesc:ad721a69e5af00f6de0a549db2c785385"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 1.4 protocol event flag.  <a href="#ad721a69e5af00f6de0a549db2c785385">More...</a><br/></td></tr>
<tr class="separator:ad721a69e5af00f6de0a549db2c785385"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae66d1d1e4f9cd148f963251c5721ae7f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ae66d1d1e4f9cd148f963251c5721ae7f">XV_HDMIRX_DDC_STA_HDCP_2_PROT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:ae66d1d1e4f9cd148f963251c5721ae7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 protocol event flag.  <a href="#ae66d1d1e4f9cd148f963251c5721ae7f">More...</a><br/></td></tr>
<tr class="separator:ae66d1d1e4f9cd148f963251c5721ae7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af604d47ae26f7f564092cf94e9cb85d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af604d47ae26f7f564092cf94e9cb85d8">XV_HDMIRX_DDC_STA_EDID_WORDS_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:af604d47ae26f7f564092cf94e9cb85d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status EDID words shift.  <a href="#af604d47ae26f7f564092cf94e9cb85d8">More...</a><br/></td></tr>
<tr class="separator:af604d47ae26f7f564092cf94e9cb85d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6f7e2758e963a54d5dfb9152ab55a9a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a6f7e2758e963a54d5dfb9152ab55a9a0">XV_HDMIRX_DDC_STA_EDID_WORDS_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a6f7e2758e963a54d5dfb9152ab55a9a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status EDID words mask.  <a href="#a6f7e2758e963a54d5dfb9152ab55a9a0">More...</a><br/></td></tr>
<tr class="separator:a6f7e2758e963a54d5dfb9152ab55a9a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a364015db506a68de44778c9bd34c081e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a364015db506a68de44778c9bd34c081e">XV_HDMIRX_DDC_STA_HDCP_WMSG_WORDS_MASK</a>&#160;&#160;&#160;0x7FF</td></tr>
<tr class="memdesc:a364015db506a68de44778c9bd34c081e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 write message buffer words mask.  <a href="#a364015db506a68de44778c9bd34c081e">More...</a><br/></td></tr>
<tr class="separator:a364015db506a68de44778c9bd34c081e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a87098e726a4f0f15c69fa3fff49cf5c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a87098e726a4f0f15c69fa3fff49cf5c2">XV_HDMIRX_DDC_STA_HDCP_WMSG_WORDS_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a87098e726a4f0f15c69fa3fff49cf5c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 write message buffer words shift.  <a href="#a87098e726a4f0f15c69fa3fff49cf5c2">More...</a><br/></td></tr>
<tr class="separator:a87098e726a4f0f15c69fa3fff49cf5c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6d5995d1a4d8d19ede4fb69ad8130eac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a6d5995d1a4d8d19ede4fb69ad8130eac">XV_HDMIRX_DDC_STA_HDCP_WMSG_EP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;11)</td></tr>
<tr class="memdesc:a6d5995d1a4d8d19ede4fb69ad8130eac"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 write message buffer empty mask.  <a href="#a6d5995d1a4d8d19ede4fb69ad8130eac">More...</a><br/></td></tr>
<tr class="separator:a6d5995d1a4d8d19ede4fb69ad8130eac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a64024b1389da182f45323458cf1498d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a64024b1389da182f45323458cf1498d3">XV_HDMIRX_DDC_STA_HDCP_RMSG_WORDS_MASK</a>&#160;&#160;&#160;0x7FF</td></tr>
<tr class="memdesc:a64024b1389da182f45323458cf1498d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 read message buffer words mask.  <a href="#a64024b1389da182f45323458cf1498d3">More...</a><br/></td></tr>
<tr class="separator:a64024b1389da182f45323458cf1498d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1f53e7a0221d509783bfbdb538dc6f37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a1f53e7a0221d509783bfbdb538dc6f37">XV_HDMIRX_DDC_STA_HDCP_RMSG_WORDS_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a1f53e7a0221d509783bfbdb538dc6f37"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 read message buffer words shift.  <a href="#a1f53e7a0221d509783bfbdb538dc6f37">More...</a><br/></td></tr>
<tr class="separator:a1f53e7a0221d509783bfbdb538dc6f37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a321b4e4dc6951519245480d9597a2480"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a321b4e4dc6951519245480d9597a2480">XV_HDMIRX_DDC_STA_HDCP_RMSG_EP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;27)</td></tr>
<tr class="memdesc:a321b4e4dc6951519245480d9597a2480"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 read message buffer empty mask.  <a href="#a321b4e4dc6951519245480d9597a2480">More...</a><br/></td></tr>
<tr class="separator:a321b4e4dc6951519245480d9597a2480"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa81442ef4d9a2c67d81e27b171524741"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aa81442ef4d9a2c67d81e27b171524741">XV_HDMIRX_AUX_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(0*4))</td></tr>
<tr class="memdesc:aa81442ef4d9a2c67d81e27b171524741"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Identification Register offset.  <a href="#aa81442ef4d9a2c67d81e27b171524741">More...</a><br/></td></tr>
<tr class="separator:aa81442ef4d9a2c67d81e27b171524741"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1d5dd828751e58c1acd0efa6cb37cf63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a1d5dd828751e58c1acd0efa6cb37cf63">XV_HDMIRX_AUX_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(1*4))</td></tr>
<tr class="memdesc:a1d5dd828751e58c1acd0efa6cb37cf63"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register offset.  <a href="#a1d5dd828751e58c1acd0efa6cb37cf63">More...</a><br/></td></tr>
<tr class="separator:a1d5dd828751e58c1acd0efa6cb37cf63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae1e6cac9e393cbaa0fff3c768e05a6ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ae1e6cac9e393cbaa0fff3c768e05a6ce">XV_HDMIRX_AUX_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(2*4))</td></tr>
<tr class="memdesc:ae1e6cac9e393cbaa0fff3c768e05a6ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register Set offset.  <a href="#ae1e6cac9e393cbaa0fff3c768e05a6ce">More...</a><br/></td></tr>
<tr class="separator:ae1e6cac9e393cbaa0fff3c768e05a6ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3a6b7a9edc5ba9bed414a654b4a92cf3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a3a6b7a9edc5ba9bed414a654b4a92cf3">XV_HDMIRX_AUX_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(3*4))</td></tr>
<tr class="memdesc:a3a6b7a9edc5ba9bed414a654b4a92cf3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register Clear offset.  <a href="#a3a6b7a9edc5ba9bed414a654b4a92cf3">More...</a><br/></td></tr>
<tr class="separator:a3a6b7a9edc5ba9bed414a654b4a92cf3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a73d86d2cff54ce9143501c9029b6666e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a73d86d2cff54ce9143501c9029b6666e">XV_HDMIRX_AUX_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(4*4))</td></tr>
<tr class="memdesc:a73d86d2cff54ce9143501c9029b6666e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Register offset.  <a href="#a73d86d2cff54ce9143501c9029b6666e">More...</a><br/></td></tr>
<tr class="separator:a73d86d2cff54ce9143501c9029b6666e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac80a617f8a5b2b43b099c0b500578b32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ac80a617f8a5b2b43b099c0b500578b32">XV_HDMIRX_AUX_DAT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(5*4))</td></tr>
<tr class="memdesc:ac80a617f8a5b2b43b099c0b500578b32"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Data Register offset.  <a href="#ac80a617f8a5b2b43b099c0b500578b32">More...</a><br/></td></tr>
<tr class="separator:ac80a617f8a5b2b43b099c0b500578b32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b8f81778779480d71ed771ec5a98610"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a0b8f81778779480d71ed771ec5a98610">XV_HDMIRX_AUX_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a0b8f81778779480d71ed771ec5a98610"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Run mask.  <a href="#a0b8f81778779480d71ed771ec5a98610">More...</a><br/></td></tr>
<tr class="separator:a0b8f81778779480d71ed771ec5a98610"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab1b73383c2d1aa43815eb0431f3016df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab1b73383c2d1aa43815eb0431f3016df">XV_HDMIRX_AUX_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ab1b73383c2d1aa43815eb0431f3016df"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Interrupt Enable mask.  <a href="#ab1b73383c2d1aa43815eb0431f3016df">More...</a><br/></td></tr>
<tr class="separator:ab1b73383c2d1aa43815eb0431f3016df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeb2ba5951bb5bc0f1db1840deac5652f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aeb2ba5951bb5bc0f1db1840deac5652f">XV_HDMIRX_AUX_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aeb2ba5951bb5bc0f1db1840deac5652f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Interrupt mask.  <a href="#aeb2ba5951bb5bc0f1db1840deac5652f">More...</a><br/></td></tr>
<tr class="separator:aeb2ba5951bb5bc0f1db1840deac5652f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:addf6d2a2c6904375b30d86097b2818f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#addf6d2a2c6904375b30d86097b2818f3">XV_HDMIRX_AUX_STA_NEW_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:addf6d2a2c6904375b30d86097b2818f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status New Packet mask.  <a href="#addf6d2a2c6904375b30d86097b2818f3">More...</a><br/></td></tr>
<tr class="separator:addf6d2a2c6904375b30d86097b2818f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab3618d48631462784292ed06e75d02a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab3618d48631462784292ed06e75d02a0">XV_HDMIRX_AUX_STA_ERR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:ab3618d48631462784292ed06e75d02a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status New Packet mask.  <a href="#ab3618d48631462784292ed06e75d02a0">More...</a><br/></td></tr>
<tr class="separator:ab3618d48631462784292ed06e75d02a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2a2964d1f987bbdb5055dc4afeb66c0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a2a2964d1f987bbdb5055dc4afeb66c0a">XV_HDMIRX_AUX_STA_AVI_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a2a2964d1f987bbdb5055dc4afeb66c0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI infoframe mask.  <a href="#a2a2964d1f987bbdb5055dc4afeb66c0a">More...</a><br/></td></tr>
<tr class="separator:a2a2964d1f987bbdb5055dc4afeb66c0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6968421b806da48906fe3e766f3d0cc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a6968421b806da48906fe3e766f3d0cc4">XV_HDMIRX_AUX_STA_GCP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a6968421b806da48906fe3e766f3d0cc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status General control packet mask.  <a href="#a6968421b806da48906fe3e766f3d0cc4">More...</a><br/></td></tr>
<tr class="separator:a6968421b806da48906fe3e766f3d0cc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae26445a2639c20903f9dd19eded90014"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ae26445a2639c20903f9dd19eded90014">XV_HDMIRX_AUX_STA_FIFO_EP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:ae26445a2639c20903f9dd19eded90014"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Empty mask.  <a href="#ae26445a2639c20903f9dd19eded90014">More...</a><br/></td></tr>
<tr class="separator:ae26445a2639c20903f9dd19eded90014"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a031ed61017975ae43a74b82e80a499a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a031ed61017975ae43a74b82e80a499a3">XV_HDMIRX_AUX_STA_FIFO_FL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:a031ed61017975ae43a74b82e80a499a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Full mask.  <a href="#a031ed61017975ae43a74b82e80a499a3">More...</a><br/></td></tr>
<tr class="separator:a031ed61017975ae43a74b82e80a499a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a20f3cfcfccb4fa2a3cb1c8503217c08c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a20f3cfcfccb4fa2a3cb1c8503217c08c">XV_HDMIRX_AUX_STA_GCP_CD_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;25)</td></tr>
<tr class="memdesc:a20f3cfcfccb4fa2a3cb1c8503217c08c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP ColorDepth mask.  <a href="#a20f3cfcfccb4fa2a3cb1c8503217c08c">More...</a><br/></td></tr>
<tr class="separator:a20f3cfcfccb4fa2a3cb1c8503217c08c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2e4a698c7fee38a5e5a92cc9530c1c1a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a2e4a698c7fee38a5e5a92cc9530c1c1a">XV_HDMIRX_AUX_STA_GCP_AVMUTE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;31)</td></tr>
<tr class="memdesc:a2e4a698c7fee38a5e5a92cc9530c1c1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP avmute mask.  <a href="#a2e4a698c7fee38a5e5a92cc9530c1c1a">More...</a><br/></td></tr>
<tr class="separator:a2e4a698c7fee38a5e5a92cc9530c1c1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab0a13f1e1dec574124a7988bb34ca627"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab0a13f1e1dec574124a7988bb34ca627">XV_HDMIRX_AUX_STA_NEW_PKTS_MASK</a>&#160;&#160;&#160;0x1F</td></tr>
<tr class="memdesc:ab0a13f1e1dec574124a7988bb34ca627"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status New Packets mask.  <a href="#ab0a13f1e1dec574124a7988bb34ca627">More...</a><br/></td></tr>
<tr class="separator:ab0a13f1e1dec574124a7988bb34ca627"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a18c0b376a593da7df6775ebc78394355"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a18c0b376a593da7df6775ebc78394355">XV_HDMIRX_AUX_STA_AVI_CS_MASK</a>&#160;&#160;&#160;0x03</td></tr>
<tr class="memdesc:a18c0b376a593da7df6775ebc78394355"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI colorspace mask.  <a href="#a18c0b376a593da7df6775ebc78394355">More...</a><br/></td></tr>
<tr class="separator:a18c0b376a593da7df6775ebc78394355"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aae57be2d73942a73e349d3d468d4f8b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aae57be2d73942a73e349d3d468d4f8b7">XV_HDMIRX_AUX_STA_AVI_VIC_MASK</a>&#160;&#160;&#160;0x7F</td></tr>
<tr class="memdesc:aae57be2d73942a73e349d3d468d4f8b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI VIC mask.  <a href="#aae57be2d73942a73e349d3d468d4f8b7">More...</a><br/></td></tr>
<tr class="separator:aae57be2d73942a73e349d3d468d4f8b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6e84a7312408ad6204ee0846573e292c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a6e84a7312408ad6204ee0846573e292c">XV_HDMIRX_AUX_STA_GCP_CD_MASK</a>&#160;&#160;&#160;0x03</td></tr>
<tr class="memdesc:a6e84a7312408ad6204ee0846573e292c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP colordepth mask.  <a href="#a6e84a7312408ad6204ee0846573e292c">More...</a><br/></td></tr>
<tr class="separator:a6e84a7312408ad6204ee0846573e292c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9b1f3886f6d42a5d5b69a1851c77b1ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a9b1f3886f6d42a5d5b69a1851c77b1ab">XV_HDMIRX_AUX_STA_GCP_PP_MASK</a>&#160;&#160;&#160;0x07</td></tr>
<tr class="memdesc:a9b1f3886f6d42a5d5b69a1851c77b1ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP pixel phase mask.  <a href="#a9b1f3886f6d42a5d5b69a1851c77b1ab">More...</a><br/></td></tr>
<tr class="separator:a9b1f3886f6d42a5d5b69a1851c77b1ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a57a0928c7a74d34dc804de668d28cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a7a57a0928c7a74d34dc804de668d28cd">XV_HDMIRX_AUX_STA_NEW_PKTS_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a7a57a0928c7a74d34dc804de668d28cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status New Packets Shift.  <a href="#a7a57a0928c7a74d34dc804de668d28cd">More...</a><br/></td></tr>
<tr class="separator:a7a57a0928c7a74d34dc804de668d28cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac299e0cc30499f86f60267f7c23d3242"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ac299e0cc30499f86f60267f7c23d3242">XV_HDMIRX_AUX_STA_AVI_CS_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ac299e0cc30499f86f60267f7c23d3242"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI colorspace Shift.  <a href="#ac299e0cc30499f86f60267f7c23d3242">More...</a><br/></td></tr>
<tr class="separator:ac299e0cc30499f86f60267f7c23d3242"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1eac59ae54921281d77742aabb932158"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a1eac59ae54921281d77742aabb932158">XV_HDMIRX_AUX_STA_AVI_VIC_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:a1eac59ae54921281d77742aabb932158"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI VIC Shift.  <a href="#a1eac59ae54921281d77742aabb932158">More...</a><br/></td></tr>
<tr class="separator:a1eac59ae54921281d77742aabb932158"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6078073cb572492cffb23b1c85a514a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a6078073cb572492cffb23b1c85a514a2">XV_HDMIRX_AUX_STA_GCP_CD_SHIFT</a>&#160;&#160;&#160;26</td></tr>
<tr class="memdesc:a6078073cb572492cffb23b1c85a514a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP colordepth Shift.  <a href="#a6078073cb572492cffb23b1c85a514a2">More...</a><br/></td></tr>
<tr class="separator:a6078073cb572492cffb23b1c85a514a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af6f919dfe8242811589c914bb008a3e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af6f919dfe8242811589c914bb008a3e9">XV_HDMIRX_AUX_STA_GCP_PP_SHIFT</a>&#160;&#160;&#160;28</td></tr>
<tr class="memdesc:af6f919dfe8242811589c914bb008a3e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP pixel phase Shift.  <a href="#af6f919dfe8242811589c914bb008a3e9">More...</a><br/></td></tr>
<tr class="separator:af6f919dfe8242811589c914bb008a3e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa27e0e3487532f0476be811b7d95e799"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aa27e0e3487532f0476be811b7d95e799">XV_HDMIRX_AUD_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(0*4))</td></tr>
<tr class="memdesc:aa27e0e3487532f0476be811b7d95e799"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Identification Register offset.  <a href="#aa27e0e3487532f0476be811b7d95e799">More...</a><br/></td></tr>
<tr class="separator:aa27e0e3487532f0476be811b7d95e799"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add5a4bf9070b2decf5ac41ca31a4e914"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#add5a4bf9070b2decf5ac41ca31a4e914">XV_HDMIRX_AUD_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(1*4))</td></tr>
<tr class="memdesc:add5a4bf9070b2decf5ac41ca31a4e914"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register offset.  <a href="#add5a4bf9070b2decf5ac41ca31a4e914">More...</a><br/></td></tr>
<tr class="separator:add5a4bf9070b2decf5ac41ca31a4e914"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9428f4a8196d2f0576ba5ea841037f6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a9428f4a8196d2f0576ba5ea841037f6b">XV_HDMIRX_AUD_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(2*4))</td></tr>
<tr class="memdesc:a9428f4a8196d2f0576ba5ea841037f6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register Set offset.  <a href="#a9428f4a8196d2f0576ba5ea841037f6b">More...</a><br/></td></tr>
<tr class="separator:a9428f4a8196d2f0576ba5ea841037f6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab9b4d72b50e6d6bfb3d5a570c8d172b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab9b4d72b50e6d6bfb3d5a570c8d172b3">XV_HDMIRX_AUD_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(3*4))</td></tr>
<tr class="memdesc:ab9b4d72b50e6d6bfb3d5a570c8d172b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register Clear offset.  <a href="#ab9b4d72b50e6d6bfb3d5a570c8d172b3">More...</a><br/></td></tr>
<tr class="separator:ab9b4d72b50e6d6bfb3d5a570c8d172b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaeabc64551cfb1c8e0b4451fe5b4bdaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aaeabc64551cfb1c8e0b4451fe5b4bdaf">XV_HDMIRX_AUD_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(4*4))</td></tr>
<tr class="memdesc:aaeabc64551cfb1c8e0b4451fe5b4bdaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Register offset.  <a href="#aaeabc64551cfb1c8e0b4451fe5b4bdaf">More...</a><br/></td></tr>
<tr class="separator:aaeabc64551cfb1c8e0b4451fe5b4bdaf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f83199b3cdb183ee02353d031743062"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a3f83199b3cdb183ee02353d031743062">XV_HDMIRX_AUD_CTS_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(5*4))</td></tr>
<tr class="memdesc:a3f83199b3cdb183ee02353d031743062"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD CTS Register offset.  <a href="#a3f83199b3cdb183ee02353d031743062">More...</a><br/></td></tr>
<tr class="separator:a3f83199b3cdb183ee02353d031743062"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0c222588615d7174edf1b8c474675ec3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a0c222588615d7174edf1b8c474675ec3">XV_HDMIRX_AUD_N_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(6*4))</td></tr>
<tr class="memdesc:a0c222588615d7174edf1b8c474675ec3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD N Register offset.  <a href="#a0c222588615d7174edf1b8c474675ec3">More...</a><br/></td></tr>
<tr class="separator:a0c222588615d7174edf1b8c474675ec3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a567c57fe4410dd785a044d5bc5ffd55b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a567c57fe4410dd785a044d5bc5ffd55b">XV_HDMIRX_AUD_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a567c57fe4410dd785a044d5bc5ffd55b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Run mask.  <a href="#a567c57fe4410dd785a044d5bc5ffd55b">More...</a><br/></td></tr>
<tr class="separator:a567c57fe4410dd785a044d5bc5ffd55b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a87eaa7535d04479ccecaec7a1a97aadc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a87eaa7535d04479ccecaec7a1a97aadc">XV_HDMIRX_AUD_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a87eaa7535d04479ccecaec7a1a97aadc"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Interrupt Enable mask.  <a href="#a87eaa7535d04479ccecaec7a1a97aadc">More...</a><br/></td></tr>
<tr class="separator:a87eaa7535d04479ccecaec7a1a97aadc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a95678b96a69da93e8ed300c4d8e75475"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a95678b96a69da93e8ed300c4d8e75475">XV_HDMIRX_AUD_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a95678b96a69da93e8ed300c4d8e75475"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Interrupt mask.  <a href="#a95678b96a69da93e8ed300c4d8e75475">More...</a><br/></td></tr>
<tr class="separator:a95678b96a69da93e8ed300c4d8e75475"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d187ed36cde3cb36eeae049ad3d91f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a9d187ed36cde3cb36eeae049ad3d91f9">XV_HDMIRX_AUD_STA_ACT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a9d187ed36cde3cb36eeae049ad3d91f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Event mask.  <a href="#a9d187ed36cde3cb36eeae049ad3d91f9">More...</a><br/></td></tr>
<tr class="separator:a9d187ed36cde3cb36eeae049ad3d91f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab307264da6388cded12f39f3c7a24732"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab307264da6388cded12f39f3c7a24732">XV_HDMIRX_AUD_STA_CH_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:ab307264da6388cded12f39f3c7a24732"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Event mask.  <a href="#ab307264da6388cded12f39f3c7a24732">More...</a><br/></td></tr>
<tr class="separator:ab307264da6388cded12f39f3c7a24732"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a98ca2ff777b73ff293379306f5f57b8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a98ca2ff777b73ff293379306f5f57b8e">XV_HDMIRX_AUD_STA_ACT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a98ca2ff777b73ff293379306f5f57b8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Active mask.  <a href="#a98ca2ff777b73ff293379306f5f57b8e">More...</a><br/></td></tr>
<tr class="separator:a98ca2ff777b73ff293379306f5f57b8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a292e4fe82c8bbaecd8e3a0982762d557"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a292e4fe82c8bbaecd8e3a0982762d557">XV_HDMIRX_AUD_STA_AUD_CH_MASK</a>&#160;&#160;&#160;0x1F</td></tr>
<tr class="memdesc:a292e4fe82c8bbaecd8e3a0982762d557"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio channel mask.  <a href="#a292e4fe82c8bbaecd8e3a0982762d557">More...</a><br/></td></tr>
<tr class="separator:a292e4fe82c8bbaecd8e3a0982762d557"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4a7eab9bd6be6a6ba673e6f5a959dea7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a4a7eab9bd6be6a6ba673e6f5a959dea7">XV_HDMIRX_AUD_STA_AUD_CH_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a4a7eab9bd6be6a6ba673e6f5a959dea7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio channel Shift.  <a href="#a4a7eab9bd6be6a6ba673e6f5a959dea7">More...</a><br/></td></tr>
<tr class="separator:a4a7eab9bd6be6a6ba673e6f5a959dea7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4a1038421efd5ff07accc769019102e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ad4a1038421efd5ff07accc769019102e">XV_HDMIRX_AUD_STA_AUD_FMT_MASK</a>&#160;&#160;&#160;0x07</td></tr>
<tr class="memdesc:ad4a1038421efd5ff07accc769019102e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio Format mask.  <a href="#ad4a1038421efd5ff07accc769019102e">More...</a><br/></td></tr>
<tr class="separator:ad4a1038421efd5ff07accc769019102e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7896f888d03cc5cd46c5c869ccfc5421"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a7896f888d03cc5cd46c5c869ccfc5421">XV_HDMIRX_AUD_STA_AUD_FMT_SHIFT</a>&#160;&#160;&#160;13</td></tr>
<tr class="memdesc:a7896f888d03cc5cd46c5c869ccfc5421"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio Format Shift.  <a href="#a7896f888d03cc5cd46c5c869ccfc5421">More...</a><br/></td></tr>
<tr class="separator:a7896f888d03cc5cd46c5c869ccfc5421"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a940806715e55ccfd0f0813e1b64abd3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a940806715e55ccfd0f0813e1b64abd3d">XV_HDMIRX_LNKSTA_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(0*4))</td></tr>
<tr class="memdesc:a940806715e55ccfd0f0813e1b64abd3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Identification Register offset.  <a href="#a940806715e55ccfd0f0813e1b64abd3d">More...</a><br/></td></tr>
<tr class="separator:a940806715e55ccfd0f0813e1b64abd3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a81049dffe0990151a58b1728dade86f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a81049dffe0990151a58b1728dade86f4">XV_HDMIRX_LNKSTA_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(1*4))</td></tr>
<tr class="memdesc:a81049dffe0990151a58b1728dade86f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Register offset.  <a href="#a81049dffe0990151a58b1728dade86f4">More...</a><br/></td></tr>
<tr class="separator:a81049dffe0990151a58b1728dade86f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa310321ea49ca6efcd3cd727554d74df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aa310321ea49ca6efcd3cd727554d74df">XV_HDMIRX_LNKSTA_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(2*4))</td></tr>
<tr class="memdesc:aa310321ea49ca6efcd3cd727554d74df"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Register Set offset.  <a href="#aa310321ea49ca6efcd3cd727554d74df">More...</a><br/></td></tr>
<tr class="separator:aa310321ea49ca6efcd3cd727554d74df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc673f54db2a25dee45c4f1c8d321e95"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#abc673f54db2a25dee45c4f1c8d321e95">XV_HDMIRX_LNKSTA_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(3*4))</td></tr>
<tr class="memdesc:abc673f54db2a25dee45c4f1c8d321e95"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Register Clear offset.  <a href="#abc673f54db2a25dee45c4f1c8d321e95">More...</a><br/></td></tr>
<tr class="separator:abc673f54db2a25dee45c4f1c8d321e95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a99d2e4c21738838bb3de9ab7042019b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a99d2e4c21738838bb3de9ab7042019b1">XV_HDMIRX_LNKSTA_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(4*4))</td></tr>
<tr class="memdesc:a99d2e4c21738838bb3de9ab7042019b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Status Register offset.  <a href="#a99d2e4c21738838bb3de9ab7042019b1">More...</a><br/></td></tr>
<tr class="separator:a99d2e4c21738838bb3de9ab7042019b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afb0995c7dadd967e0be16f4d31d60bd8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#afb0995c7dadd967e0be16f4d31d60bd8">XV_HDMIRX_LNKSTA_LNK_ERR0_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(5*4))</td></tr>
<tr class="memdesc:afb0995c7dadd967e0be16f4d31d60bd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Link Error Counter Channel 0 Register offset.  <a href="#afb0995c7dadd967e0be16f4d31d60bd8">More...</a><br/></td></tr>
<tr class="separator:afb0995c7dadd967e0be16f4d31d60bd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a06437de32dc8a09506cd5513a8fc66ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a06437de32dc8a09506cd5513a8fc66ac">XV_HDMIRX_LNKSTA_LNK_ERR1_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(6*4))</td></tr>
<tr class="memdesc:a06437de32dc8a09506cd5513a8fc66ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Link Error Counter Channel 1 Register offset.  <a href="#a06437de32dc8a09506cd5513a8fc66ac">More...</a><br/></td></tr>
<tr class="separator:a06437de32dc8a09506cd5513a8fc66ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a65b7bcbf5858f0f7786c8ca1322eb33e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a65b7bcbf5858f0f7786c8ca1322eb33e">XV_HDMIRX_LNKSTA_LNK_ERR2_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(7*4))</td></tr>
<tr class="memdesc:a65b7bcbf5858f0f7786c8ca1322eb33e"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Link Error Counter Channel 2 Register offset.  <a href="#a65b7bcbf5858f0f7786c8ca1322eb33e">More...</a><br/></td></tr>
<tr class="separator:a65b7bcbf5858f0f7786c8ca1322eb33e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9be02907eee90b0290839d85acc6818c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a9be02907eee90b0290839d85acc6818c">XV_HDMIRX_LNKSTA_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a9be02907eee90b0290839d85acc6818c"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Run mask.  <a href="#a9be02907eee90b0290839d85acc6818c">More...</a><br/></td></tr>
<tr class="separator:a9be02907eee90b0290839d85acc6818c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab0f62d22721883dd2d740b4edbf6872a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab0f62d22721883dd2d740b4edbf6872a">XV_HDMIRX_LNKSTA_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ab0f62d22721883dd2d740b4edbf6872a"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Interrupt Enable mask.  <a href="#ab0f62d22721883dd2d740b4edbf6872a">More...</a><br/></td></tr>
<tr class="separator:ab0f62d22721883dd2d740b4edbf6872a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa6d26913bac16d95ae5a5af1173ccb13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aa6d26913bac16d95ae5a5af1173ccb13">XV_HDMIRX_LNKSTA_CTRL_ERR_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:aa6d26913bac16d95ae5a5af1173ccb13"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Error Clear mask.  <a href="#aa6d26913bac16d95ae5a5af1173ccb13">More...</a><br/></td></tr>
<tr class="separator:aa6d26913bac16d95ae5a5af1173ccb13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af50dcf2fedf4c2d07147f47e4bb64037"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#af50dcf2fedf4c2d07147f47e4bb64037">XV_HDMIRX_LNKSTA_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:af50dcf2fedf4c2d07147f47e4bb64037"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Status Interrupt mask.  <a href="#af50dcf2fedf4c2d07147f47e4bb64037">More...</a><br/></td></tr>
<tr class="separator:af50dcf2fedf4c2d07147f47e4bb64037"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6b68f41c0790de0b711903449a1286b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a6b68f41c0790de0b711903449a1286b2">XV_HDMIRX_LNKSTA_STA_ERR_MAX_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a6b68f41c0790de0b711903449a1286b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Status Maximum Errors mask.  <a href="#a6b68f41c0790de0b711903449a1286b2">More...</a><br/></td></tr>
<tr class="separator:a6b68f41c0790de0b711903449a1286b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58ff62ffa6d07e198733b7ef576f2ac3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a58ff62ffa6d07e198733b7ef576f2ac3">XV_HDMIRX_SHIFT_16</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a58ff62ffa6d07e198733b7ef576f2ac3"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 shift value  <a href="#a58ff62ffa6d07e198733b7ef576f2ac3">More...</a><br/></td></tr>
<tr class="separator:a58ff62ffa6d07e198733b7ef576f2ac3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4a6303e5aa23e44351563d3559d9a7cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a4a6303e5aa23e44351563d3559d9a7cc">XV_HDMIRX_MASK_16</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a4a6303e5aa23e44351563d3559d9a7cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 bit mask value  <a href="#a4a6303e5aa23e44351563d3559d9a7cc">More...</a><br/></td></tr>
<tr class="separator:a4a6303e5aa23e44351563d3559d9a7cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3b2aba60044d1ec3e9ddfc0172f77141"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a3b2aba60044d1ec3e9ddfc0172f77141">XV_HDMIRX_PIO_ID</a>&#160;&#160;&#160;0x2200</td></tr>
<tr class="memdesc:a3b2aba60044d1ec3e9ddfc0172f77141"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO ID.  <a href="#a3b2aba60044d1ec3e9ddfc0172f77141">More...</a><br/></td></tr>
<tr class="separator:a3b2aba60044d1ec3e9ddfc0172f77141"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a332d931d6e1f46b32ecd1e4ef6229dae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a332d931d6e1f46b32ecd1e4ef6229dae">XV_HDMIRX_SCDC_BRAM_OFFSET</a>&#160;&#160;&#160;0x138</td></tr>
<tr class="memdesc:a332d931d6e1f46b32ecd1e4ef6229dae"><td class="mdescLeft">&#160;</td><td class="mdescRight">SCDC BRAM Offset.  <a href="#a332d931d6e1f46b32ecd1e4ef6229dae">More...</a><br/></td></tr>
<tr class="separator:a332d931d6e1f46b32ecd1e4ef6229dae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:ac1f9ae7bd366a3fe5db4faa53b58e4af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ac1f9ae7bd366a3fe5db4faa53b58e4af">XV_HdmiRx_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:ac1f9ae7bd366a3fe5db4faa53b58e4af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="#ac1f9ae7bd366a3fe5db4faa53b58e4af">More...</a><br/></td></tr>
<tr class="separator:ac1f9ae7bd366a3fe5db4faa53b58e4af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aed43ceb241150a4219514143f8473a4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#aed43ceb241150a4219514143f8473a4d">XV_HdmiRx_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:aed43ceb241150a4219514143f8473a4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="#aed43ceb241150a4219514143f8473a4d">More...</a><br/></td></tr>
<tr class="separator:aed43ceb241150a4219514143f8473a4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab1245a8a62b2b5611cc4cbb2aa4af75b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab1245a8a62b2b5611cc4cbb2aa4af75b">XV_HdmiRx_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="xv__hdmirx__hw_8h.html#ac1f9ae7bd366a3fe5db4faa53b58e4af">XV_HdmiRx_In32</a>((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ab1245a8a62b2b5611cc4cbb2aa4af75b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a HDMI RX register.  <a href="#ab1245a8a62b2b5611cc4cbb2aa4af75b">More...</a><br/></td></tr>
<tr class="separator:ab1245a8a62b2b5611cc4cbb2aa4af75b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a407dbf36f2752c30d265e3a8a25d29fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a407dbf36f2752c30d265e3a8a25d29fe">XV_HdmiRx_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="xv__hdmirx__hw_8h.html#aed43ceb241150a4219514143f8473a4d">XV_HdmiRx_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:a407dbf36f2752c30d265e3a8a25d29fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a HDMI RX register.  <a href="#a407dbf36f2752c30d265e3a8a25d29fe">More...</a><br/></td></tr>
<tr class="separator:a407dbf36f2752c30d265e3a8a25d29fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ab9b4d72b50e6d6bfb3d5a570c8d172b3"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(3*4))</td>
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</div><div class="memdoc">

<p>AUD Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a87eaa7535d04479ccecaec7a1a97aadc"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
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<p>AUD Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="add5a4bf9070b2decf5ac41ca31a4e914"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(1*4))</td>
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</div><div class="memdoc">

<p>AUD Control Register offset. </p>

</div>
</div>
<a class="anchor" id="a567c57fe4410dd785a044d5bc5ffd55b"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
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<p>AUD Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a9428f4a8196d2f0576ba5ea841037f6b"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(2*4))</td>
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</div><div class="memdoc">

<p>AUD Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="a3f83199b3cdb183ee02353d031743062"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_CTS_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(5*4))</td>
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<p>AUD CTS Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ae3dcd032d351867697f19280fdeb1eeb">XV_HdmiRx_GetAcrCts()</a>.</p>

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</div>
<a class="anchor" id="aa27e0e3487532f0476be811b7d95e799"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(0*4))</td>
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</div><div class="memdoc">

<p>AUD Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a0c222588615d7174edf1b8c474675ec3"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_N_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(6*4))</td>
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<p>AUD N Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a0b9483d540e72c619bcc9ba5d516ebe8">XV_HdmiRx_GetAcrN()</a>.</p>

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</div>
<a class="anchor" id="a9d187ed36cde3cb36eeae049ad3d91f9"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_STA_ACT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
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      </table>
</div><div class="memdoc">

<p>AUD Status Event mask. </p>

</div>
</div>
<a class="anchor" id="a98ca2ff777b73ff293379306f5f57b8e"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_STA_ACT_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
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<p>AUD Status Active mask. </p>

</div>
</div>
<a class="anchor" id="a292e4fe82c8bbaecd8e3a0982762d557"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_STA_AUD_CH_MASK&#160;&#160;&#160;0x1F</td>
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</div><div class="memdoc">

<p>AUD Status Audio channel mask. </p>

</div>
</div>
<a class="anchor" id="a4a7eab9bd6be6a6ba673e6f5a959dea7"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_STA_AUD_CH_SHIFT&#160;&#160;&#160;8</td>
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<p>AUD Status Audio channel Shift. </p>

</div>
</div>
<a class="anchor" id="ad4a1038421efd5ff07accc769019102e"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_STA_AUD_FMT_MASK&#160;&#160;&#160;0x07</td>
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<p>AUD Status Audio Format mask. </p>

</div>
</div>
<a class="anchor" id="a7896f888d03cc5cd46c5c869ccfc5421"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_STA_AUD_FMT_SHIFT&#160;&#160;&#160;13</td>
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      </table>
</div><div class="memdoc">

<p>AUD Status Audio Format Shift. </p>

</div>
</div>
<a class="anchor" id="ab307264da6388cded12f39f3c7a24732"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_STA_CH_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
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      </table>
</div><div class="memdoc">

<p>AUD Status Event mask. </p>

</div>
</div>
<a class="anchor" id="a95678b96a69da93e8ed300c4d8e75475"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
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<p>AUD Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="aaeabc64551cfb1c8e0b4451fe5b4bdaf"></a>
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          <td class="memname">#define XV_HDMIRX_AUD_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(4*4))</td>
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      </table>
</div><div class="memdoc">

<p>AUD Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

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</div>
<a class="anchor" id="a3a6b7a9edc5ba9bed414a654b4a92cf3"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(3*4))</td>
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      </table>
</div><div class="memdoc">

<p>AUX Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="ab1b73383c2d1aa43815eb0431f3016df"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
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      </table>
</div><div class="memdoc">

<p>AUX Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a1d5dd828751e58c1acd0efa6cb37cf63"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(1*4))</td>
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      </table>
</div><div class="memdoc">

<p>AUX Control Register offset. </p>

</div>
</div>
<a class="anchor" id="a0b8f81778779480d71ed771ec5a98610"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
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</div><div class="memdoc">

<p>AUX Control Run mask. </p>

</div>
</div>
<a class="anchor" id="ae1e6cac9e393cbaa0fff3c768e05a6ce"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(2*4))</td>
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</div><div class="memdoc">

<p>AUX Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="ac80a617f8a5b2b43b099c0b500578b32"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_DAT_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(5*4))</td>
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</div><div class="memdoc">

<p>AUX Data Register offset. </p>

</div>
</div>
<a class="anchor" id="aa81442ef4d9a2c67d81e27b171524741"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(0*4))</td>
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      </table>
</div><div class="memdoc">

<p>AUX Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a18c0b376a593da7df6775ebc78394355"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_CS_MASK&#160;&#160;&#160;0x03</td>
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</div><div class="memdoc">

<p>AUX Status AVI colorspace mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a4b2650f744a2a244482124697e632863">XV_HdmiRx_GetAviColorSpace()</a>.</p>

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</div>
<a class="anchor" id="ac299e0cc30499f86f60267f7c23d3242"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_CS_SHIFT&#160;&#160;&#160;16</td>
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</div><div class="memdoc">

<p>AUX Status AVI colorspace Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a4b2650f744a2a244482124697e632863">XV_HdmiRx_GetAviColorSpace()</a>.</p>

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</div>
<a class="anchor" id="a2a2964d1f987bbdb5055dc4afeb66c0a"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
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</div><div class="memdoc">

<p>AUX Status AVI infoframe mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a6f74899b52dfbb8e0e554bbdea04bd29">XV_HdmiRx_GetVideoProperties()</a>.</p>

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</div>
<a class="anchor" id="aae57be2d73942a73e349d3d468d4f8b7"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_VIC_MASK&#160;&#160;&#160;0x7F</td>
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<p>AUX Status AVI VIC mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#afaa89bbc453b2d7e1446140c73b7baee">XV_HdmiRx_GetAviVic()</a>.</p>

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</div>
<a class="anchor" id="a1eac59ae54921281d77742aabb932158"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_VIC_SHIFT&#160;&#160;&#160;18</td>
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      </table>
</div><div class="memdoc">

<p>AUX Status AVI VIC Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#afaa89bbc453b2d7e1446140c73b7baee">XV_HdmiRx_GetAviVic()</a>.</p>

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</div>
<a class="anchor" id="ab3618d48631462784292ed06e75d02a0"></a>
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          <td class="memname">#define XV_HDMIRX_AUX_STA_ERR_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
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<p>AUX Status New Packet mask. </p>

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<a class="anchor" id="ae26445a2639c20903f9dd19eded90014"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_FIFO_EP_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Empty mask. </p>

</div>
</div>
<a class="anchor" id="a031ed61017975ae43a74b82e80a499a3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_FIFO_FL_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Full mask. </p>

</div>
</div>
<a class="anchor" id="a2e4a698c7fee38a5e5a92cc9530c1c1a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_AVMUTE_MASK&#160;&#160;&#160;(1&lt;&lt;31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP avmute mask. </p>

</div>
</div>
<a class="anchor" id="a20f3cfcfccb4fa2a3cb1c8503217c08c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_CD_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;25)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP ColorDepth mask. </p>

</div>
</div>
<a class="anchor" id="a6e84a7312408ad6204ee0846573e292c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_CD_MASK&#160;&#160;&#160;0x03</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP colordepth mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a87e0904b6a6167f3cde2e7fcc0843e1d">XV_HdmiRx_GetGcpColorDepth()</a>.</p>

</div>
</div>
<a class="anchor" id="a6078073cb572492cffb23b1c85a514a2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_CD_SHIFT&#160;&#160;&#160;26</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP colordepth Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a87e0904b6a6167f3cde2e7fcc0843e1d">XV_HdmiRx_GetGcpColorDepth()</a>.</p>

</div>
</div>
<a class="anchor" id="a6968421b806da48906fe3e766f3d0cc4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status General control packet mask. </p>

</div>
</div>
<a class="anchor" id="a9b1f3886f6d42a5d5b69a1851c77b1ab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_PP_MASK&#160;&#160;&#160;0x07</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP pixel phase mask. </p>

</div>
</div>
<a class="anchor" id="af6f919dfe8242811589c914bb008a3e9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_PP_SHIFT&#160;&#160;&#160;28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP pixel phase Shift. </p>

</div>
</div>
<a class="anchor" id="aeb2ba5951bb5bc0f1db1840deac5652f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="addf6d2a2c6904375b30d86097b2818f3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_NEW_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status New Packet mask. </p>

</div>
</div>
<a class="anchor" id="ab0a13f1e1dec574124a7988bb34ca627"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_NEW_PKTS_MASK&#160;&#160;&#160;0x1F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status New Packets mask. </p>

</div>
</div>
<a class="anchor" id="a7a57a0928c7a74d34dc804de668d28cd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_NEW_PKTS_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status New Packets Shift. </p>

</div>
</div>
<a class="anchor" id="a73d86d2cff54ce9143501c9029b6666e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a4b2650f744a2a244482124697e632863">XV_HdmiRx_GetAviColorSpace()</a>, <a class="el" href="xv__hdmirx_8h.html#afaa89bbc453b2d7e1446140c73b7baee">XV_HdmiRx_GetAviVic()</a>, <a class="el" href="xv__hdmirx_8h.html#a87e0904b6a6167f3cde2e7fcc0843e1d">XV_HdmiRx_GetGcpColorDepth()</a>, <a class="el" href="xv__hdmirx_8h.html#a6f74899b52dfbb8e0e554bbdea04bd29">XV_HdmiRx_GetVideoProperties()</a>, and <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ac5fcd5ad68b451baf56e90de899e7ede"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a92855dc688a9f79d080f1eab92e17144"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_EDID_EN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control EDID enable mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a937baab4a62131f510e87602c5e5f669"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_HDCP_EN_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control HDCP enable mask. </p>

</div>
</div>
<a class="anchor" id="ab8ef6708fce427ed656a9a7c2c0f8e63"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_HDCP_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control HDCP mode mask. </p>

</div>
</div>
<a class="anchor" id="acda38629aa70cc313c59ba64eb8e3318"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Interrupt enable mask. </p>

</div>
</div>
<a class="anchor" id="a7a103df1d10146f4676b28638b418bca"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register offset. </p>

</div>
</div>
<a class="anchor" id="af8e7afbf29117f39c72339d26872246a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_RMSG_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control read message clear mask. </p>

</div>
</div>
<a class="anchor" id="a91f5315d7efd6486cef6ed81161c1411"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a2fcc95a6129eacc331e014e496db9031"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_SCDC_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control SCDC clear mask. </p>

</div>
</div>
<a class="anchor" id="a70913fe092b1adef31afb152cd679de3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_SCDC_EN_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control SCDC enable mask. </p>

</div>
</div>
<a class="anchor" id="a8272d8237c5560511743f6645351c889"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a0210e2d1fa6287ae916903a548246052"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_WMSG_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control write message clear mask. </p>

</div>
</div>
<a class="anchor" id="a87d82ea13dd71da7ed87b4645b056dd5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_EDID_DATA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID data offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a8b682b85fe84e6b981cd441bc1e737c1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_EDID_RP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID read pointer offset. </p>

</div>
</div>
<a class="anchor" id="a659ddc496ff647b94aab4c2e401eb131"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_EDID_SP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID segment pointer offset. </p>

</div>
</div>
<a class="anchor" id="a353a7e74a37ccc5fe06e7dfbf1d1e05d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_EDID_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC EDID Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8c.html#a0ede81f7ab3357d5fe81c8df0f125e27">XV_HdmiRx_DdcGetEdidWords()</a>.</p>

</div>
</div>
<a class="anchor" id="abd5e2bee6eb83de864de63600afef44d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_EDID_WP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID write pointer offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a6b100412180e030ef95cb8ecaa5934b3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_HDCP_ADDRESS_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read HDCP address offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a7d5ad8989577d890a1df04c252daa478">XV_HdmiRx_DdcHdcpSetAddress()</a>.</p>

</div>
</div>
<a class="anchor" id="acc2e9a9d6af18df813b60237a319900a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_HDCP_DATA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read HDCP data offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a17547b4a343f0d8a57728948d063ef90">XV_HdmiRx_DdcHdcpReadData()</a>, and <a class="el" href="xv__hdmirx_8h.html#a7cc9095feabfbd561eeb22c90f793a7b">XV_HdmiRx_DdcHdcpWriteData()</a>.</p>

</div>
</div>
<a class="anchor" id="af496088efcd5b696f2c6a53b19c73679"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_HDCP_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC HDCP Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a257f8ee397eb2b80be3bd776c4120320">XV_HdmiRx_DdcGetHdcpReadMessageBufferWords()</a>, <a class="el" href="xv__hdmirx_8h.html#a5d6a4d5464644a04891aaa68c3343edb">XV_HdmiRx_DdcGetHdcpWriteMessageBufferWords()</a>, <a class="el" href="xv__hdmirx_8h.html#a6118306bb3bc6821b5a87640a34cafcc">XV_HdmiRx_DdcIsHdcpReadMessageBufferEmpty()</a>, and <a class="el" href="xv__hdmirx_8h.html#a974d5daca9913663c9752972d3953ba4">XV_HdmiRx_DdcIsHdcpWriteMessageBufferEmpty()</a>.</p>

</div>
</div>
<a class="anchor" id="ad73e990f64f6dd2501e19b8ec873f26a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="aeb8c90015c1fe7b50a3c5707aad8c259"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_BUSY_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Busy mask. </p>

</div>
</div>
<a class="anchor" id="a6f7e2758e963a54d5dfb9152ab55a9a0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_EDID_WORDS_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status EDID words mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8c.html#a0ede81f7ab3357d5fe81c8df0f125e27">XV_HdmiRx_DdcGetEdidWords()</a>.</p>

</div>
</div>
<a class="anchor" id="af604d47ae26f7f564092cf94e9cb85d8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_EDID_WORDS_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status EDID words shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8c.html#a0ede81f7ab3357d5fe81c8df0f125e27">XV_HdmiRx_DdcGetEdidWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a6ea0539a870ea8cf811427f6161820aa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Event mask. </p>

</div>
</div>
<a class="anchor" id="ad721a69e5af00f6de0a549db2c785385"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_1_PROT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 1.4 protocol event flag. </p>

</div>
</div>
<a class="anchor" id="ac3a39ab59bd30321754bf64a2c69bfca"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_1_PROT_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 1.4 protocol flag. </p>

</div>
</div>
<a class="anchor" id="ae66d1d1e4f9cd148f963251c5721ae7f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_2_PROT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 protocol event flag. </p>

</div>
</div>
<a class="anchor" id="a0b4f8b5dd134ed31ef8e417d18f75ecf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_2_PROT_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 protocol flag. </p>

</div>
</div>
<a class="anchor" id="af0335ac9bfb482b90c413e7e7d4d65e8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP AKSV event mask. </p>

</div>
</div>
<a class="anchor" id="a05164fc716abd92dac3e68f6c3155dba"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP read message buffer end event mask. </p>

</div>
</div>
<a class="anchor" id="a321b4e4dc6951519245480d9597a2480"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_RMSG_EP_MASK&#160;&#160;&#160;(1&lt;&lt;27)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 read message buffer empty mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a6118306bb3bc6821b5a87640a34cafcc">XV_HdmiRx_DdcIsHdcpReadMessageBufferEmpty()</a>.</p>

</div>
</div>
<a class="anchor" id="af1dae57555c3bf8b0ae6e23ec0246335"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP read message buffer not completed event mask. </p>

</div>
</div>
<a class="anchor" id="a64024b1389da182f45323458cf1498d3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_RMSG_WORDS_MASK&#160;&#160;&#160;0x7FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 read message buffer words mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a257f8ee397eb2b80be3bd776c4120320">XV_HdmiRx_DdcGetHdcpReadMessageBufferWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a1f53e7a0221d509783bfbdb538dc6f37"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_RMSG_WORDS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 read message buffer words shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a257f8ee397eb2b80be3bd776c4120320">XV_HdmiRx_DdcGetHdcpReadMessageBufferWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a6d5995d1a4d8d19ede4fb69ad8130eac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_WMSG_EP_MASK&#160;&#160;&#160;(1&lt;&lt;11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 write message buffer empty mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a974d5daca9913663c9752972d3953ba4">XV_HdmiRx_DdcIsHdcpWriteMessageBufferEmpty()</a>.</p>

</div>
</div>
<a class="anchor" id="a252423ec30ee3265d9a030570410bb31"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP write message buffer new event mask. </p>

</div>
</div>
<a class="anchor" id="a364015db506a68de44778c9bd34c081e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_WMSG_WORDS_MASK&#160;&#160;&#160;0x7FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 write message buffer words mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a5d6a4d5464644a04891aaa68c3343edb">XV_HdmiRx_DdcGetHdcpWriteMessageBufferWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a87098e726a4f0f15c69fa3fff49cf5c2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_WMSG_WORDS_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 write message buffer words shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a5d6a4d5464644a04891aaa68c3343edb">XV_HdmiRx_DdcGetHdcpWriteMessageBufferWords()</a>.</p>

</div>
</div>
<a class="anchor" id="aeacfe034e74301f0f50846e09966266f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a2549440290b1505f595c0986c5fe6f13"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a343d84b77859271fd326e2e8e8050fcd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_SCL_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status state of the SCL input mask. </p>

</div>
</div>
<a class="anchor" id="af2cb844892744258e47f631cc8f1ef59"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_SDA_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status state of the SDA input mask. </p>

</div>
</div>
<a class="anchor" id="ab35e8d251d6f95ff5b39b18eb7b3ef03"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="ac1f9ae7bd366a3fe5db4faa53b58e4af"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Input Operations. </p>

</div>
</div>
<a class="anchor" id="abc673f54db2a25dee45c4f1c8d321e95"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Register Clear offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ac1b7e27bd3874e33114b2e0210f54d4c">XV_HdmiRx_ClearLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="aa6d26913bac16d95ae5a5af1173ccb13"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_ERR_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Error Clear mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ac1b7e27bd3874e33114b2e0210f54d4c">XV_HdmiRx_ClearLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="ab0f62d22721883dd2d740b4edbf6872a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a81049dffe0990151a58b1728dade86f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Register offset. </p>

</div>
</div>
<a class="anchor" id="a9be02907eee90b0290839d85acc6818c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Run mask. </p>

</div>
</div>
<a class="anchor" id="aa310321ea49ca6efcd3cd727554d74df"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ac1b7e27bd3874e33114b2e0210f54d4c">XV_HdmiRx_ClearLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="a940806715e55ccfd0f0813e1b64abd3d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="afb0995c7dadd967e0be16f4d31d60bd8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_LNK_ERR0_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Link Error Counter Channel 0 Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#aad02ea3d99f0ac3a7f4a0b18f88d62e8">XV_HdmiRx_GetLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="a06437de32dc8a09506cd5513a8fc66ac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_LNK_ERR1_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Link Error Counter Channel 1 Register offset. </p>

</div>
</div>
<a class="anchor" id="a65b7bcbf5858f0f7786c8ca1322eb33e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_LNK_ERR2_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Link Error Counter Channel 2 Register offset. </p>

</div>
</div>
<a class="anchor" id="a6b68f41c0790de0b711903449a1286b2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_STA_ERR_MAX_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Status Maximum Errors mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a70bb5419e7285a268518668fda1d70cd">XV_HdmiRx_IsLinkStatusErrMax()</a>.</p>

</div>
</div>
<a class="anchor" id="af50dcf2fedf4c2d07147f47e4bb64037"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a99d2e4c21738838bb3de9ab7042019b1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>, and <a class="el" href="xv__hdmirx_8h.html#a70bb5419e7285a268518668fda1d70cd">XV_HdmiRx_IsLinkStatusErrMax()</a>.</p>

</div>
</div>
<a class="anchor" id="a4a6303e5aa23e44351563d3559d9a7cc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_MASK_16&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 bit mask value </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="aed43ceb241150a4219514143f8473a4d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output Operations. </p>

</div>
</div>
<a class="anchor" id="afd049a051639c6315d1da85f2c96e1db"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a6bda9bcf1d7cf49a93827bf03eea2e4a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a1687fd8119ecce7ab4096ff398ba0bb7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control register offset. </p>

</div>
</div>
<a class="anchor" id="a7b7db301fdc44d8f8252475ed22f6c2f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a489d5aaf485199c1eedcbfea6f4c68ec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="a3b2aba60044d1ec3e9ddfc0172f77141"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_ID&#160;&#160;&#160;0x2200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO ID. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a3072b2f474e183f436eceb634d67a7cf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Identification register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="acd03df9d68c4ed7f25d23ee69306f407"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_ALIGNER_LOCK_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In alinger lock mask. </p>

</div>
</div>
<a class="anchor" id="aa0b106779d6898b53b151f107745c119"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMIRX_PIO_IN_BRDG_OVERFLOW_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In bridge overflow mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="aac130c5fe1e9b758f5461b5ef6cd6d22"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_DET_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In cable detect mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ae971e0400e365b9f192a1fa190a4b0fd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_EVT_FE_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Falling Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ab31f69e47fbb9567a8f3f1d1c296899b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_EVT_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Register offset. </p>

</div>
</div>
<a class="anchor" id="add0c5bcaa9260b976d6ad1b020d59d8a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_EVT_RE_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Rising Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a7f6d5c17336a530b92869fa191b8cc8f"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_LNK_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In link ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="af32e3df9ebde480b8a20e03ec37a03eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Mode mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a729bb6c385b324610317135c52298eba"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a36bca352ee91492da1392cae5ddcfa6c">XV_HdmiRx_GetTmdsClockRatio()</a>.</p>

</div>
</div>
<a class="anchor" id="a63a6b5dcd3cd49bbc464bc67f3ad36cf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCDC_SCRAMBLER_ENABLE_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In SCDC scrambler enable mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="af439412374d6713f5b5a375c54d9df68"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCDC_TMDS_CLOCK_RATIO_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In SCDC TMDS clock ratio mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx_8h.html#a36bca352ee91492da1392cae5ddcfa6c">XV_HdmiRx_GetTmdsClockRatio()</a>.</p>

</div>
</div>
<a class="anchor" id="a257587f5ad87dd0795d3891d3fda3ac6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCRAMBLER_LOCK0_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock 0 mask. </p>

</div>
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<a class="anchor" id="abf5edbd5735e21545ab367940bb59aa3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCRAMBLER_LOCK1_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock 1 mask. </p>

</div>
</div>
<a class="anchor" id="a28904b530f07081146e224cc033c3cdb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCRAMBLER_LOCK2_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock 2 mask. </p>

</div>
</div>
<a class="anchor" id="a477171cef5c2a0b4621facbb41b82eb8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_VID_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In video ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a1d084bc85a72b35776b604a1f15d24df"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_AXIS_EN_MASK&#160;&#160;&#160;0x80000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Axis Enable mask. </p>

</div>
</div>
<a class="anchor" id="a818e2b5f24ae64c160d8291e2a72bbb3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_BRIDGE_PIXEL_MASK&#160;&#160;&#160;(1&lt;&lt;30)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Bridge_Pixel drop mask. </p>

</div>
</div>
<a class="anchor" id="ade6f035d0bef0ec35894c6d90d700f16"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_BRIDGE_YUV420_MASK&#160;&#160;&#160;(1&lt;&lt;29)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Bridge_YUV420 mask. </p>

</div>
</div>
<a class="anchor" id="a80d63952308a1e96d3bfd10db732b94c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Clear offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ac7e573a18cc3fce40df684e53433ac3b">XV_HdmiRx_EXT_SYSRST()</a>, <a class="el" href="xv__hdmirx_8h.html#aee47f6ad9b1b97962b16b90ccd7ee851">XV_HdmiRx_EXT_VRST()</a>, <a class="el" href="xv__hdmirx_8h.html#ae24d729d135dccfda7ff0c9757e36181">XV_HdmiRx_INT_LRST()</a>, <a class="el" href="xv__hdmirx_8h.html#a9075952d1ee753ba1bf92ea8643359f5">XV_HdmiRx_INT_VRST()</a>, and <a class="el" href="xv__hdmirx_8h.html#a8601d159dffdd4fd77d05d248b366a54">XV_HdmiRx_SetHpd()</a>.</p>

</div>
</div>
<a class="anchor" id="a03f17ccc9e2953ac921f07446dfc9c16"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_COLOR_SPACE_MASK&#160;&#160;&#160;0xC00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="a5c1716813413cd8ca952fafe0520b782"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_COLOR_SPACE_SHIFT&#160;&#160;&#160;10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="aaa2244687e75ef859bf959aade976488"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_DEEP_COLOR_MASK&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Deep Color mask. </p>

</div>
</div>
<a class="anchor" id="ab370f0d9a89642724e7a1ad311468aff"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_DEEP_COLOR_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Deep Color shift. </p>

</div>
</div>
<a class="anchor" id="a67a9be2365d43364996b89791e0f45aa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_EXT_SYSRST_MASK&#160;&#160;&#160;(1&lt;&lt;22)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out EXT_SYSRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ac7e573a18cc3fce40df684e53433ac3b">XV_HdmiRx_EXT_SYSRST()</a>.</p>

</div>
</div>
<a class="anchor" id="a44d92cc10a5825726f4ab69f1fef3039"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_EXT_VRST_MASK&#160;&#160;&#160;(1&lt;&lt;21)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out EXT_VRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#aee47f6ad9b1b97962b16b90ccd7ee851">XV_HdmiRx_EXT_VRST()</a>.</p>

</div>
</div>
<a class="anchor" id="a51974eaab5f1447924b24e7ad9795f41"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_HPD_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Hot-Plug Detect mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8601d159dffdd4fd77d05d248b366a54">XV_HdmiRx_SetHpd()</a>.</p>

</div>
</div>
<a class="anchor" id="a218ac4dfa25332f50ef814896cbc645a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_INT_LRST_MASK&#160;&#160;&#160;(1&lt;&lt;20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out INT_LRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ae24d729d135dccfda7ff0c9757e36181">XV_HdmiRx_INT_LRST()</a>.</p>

</div>
</div>
<a class="anchor" id="a122cccfebb05738c47f29c3880fdafee"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_INT_VRST_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out INT_VRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9075952d1ee753ba1bf92ea8643359f5">XV_HdmiRx_INT_VRST()</a>.</p>

</div>
</div>
<a class="anchor" id="aebf168954f7f549697220cb79a2db0e5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_LNK_EN_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out video enable mask. </p>

</div>
</div>
<a class="anchor" id="a7e3ed781e3e5bc38c206ee7d712894c8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_MSK_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Mask Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>, and <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a21ac38c5488361502fc525c6497e922b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>, and <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a415a6510fe5c6bc29230e9c370e13985"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_PIXEL_RATE_MASK&#160;&#160;&#160;0xC0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a93050e6b1ea95d7147823e81113e6919"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_PIXEL_RATE_SHIFT&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="ae9ededc60f434b8f94a94138d0ae1770"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_RESET_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Reset mask. </p>

</div>
</div>
<a class="anchor" id="ad392d4b85c6851c8ab14735efbfb863c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_SAMPLE_RATE_MASK&#160;&#160;&#160;0x300</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate mask. </p>

</div>
</div>
<a class="anchor" id="ab7a79de3656d1b5fcaf1143c9a8ddd4d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_SAMPLE_RATE_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate shift. </p>

</div>
</div>
<a class="anchor" id="a923b78bca6113c26d4c9aa2450e12d31"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_SCRM_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Scrambler mask. </p>

</div>
</div>
<a class="anchor" id="add1b42f293960a225e7c7addc81ba41a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ac7e573a18cc3fce40df684e53433ac3b">XV_HdmiRx_EXT_SYSRST()</a>, <a class="el" href="xv__hdmirx_8h.html#aee47f6ad9b1b97962b16b90ccd7ee851">XV_HdmiRx_EXT_VRST()</a>, <a class="el" href="xv__hdmirx_8h.html#ae24d729d135dccfda7ff0c9757e36181">XV_HdmiRx_INT_LRST()</a>, <a class="el" href="xv__hdmirx_8h.html#a9075952d1ee753ba1bf92ea8643359f5">XV_HdmiRx_INT_VRST()</a>, and <a class="el" href="xv__hdmirx_8h.html#a8601d159dffdd4fd77d05d248b366a54">XV_HdmiRx_SetHpd()</a>.</p>

</div>
</div>
<a class="anchor" id="a5461b9268a85702c01115f85b1e49537"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_VID_EN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out video enable mask. </p>

</div>
</div>
<a class="anchor" id="ada79d92307e4e82afb7e7e0e477bdb8c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Event mask. </p>

</div>
</div>
<a class="anchor" id="abd3c33cf8c70cbeb50a95f7d58556579"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="af1fe9c13a0a5c613a4ca868c82c6f969"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

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</div>
<a class="anchor" id="ab1245a8a62b2b5611cc4cbb2aa4af75b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmirx__hw_8h.html#ac1f9ae7bd366a3fe5db4faa53b58e4af">XV_HdmiRx_In32</a>((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads a value from a HDMI RX register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI RX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__hdmirx__hw_8h.html#ab1245a8a62b2b5611cc4cbb2aa4af75b" title="This macro reads a value from a HDMI RX register. ">XV_HdmiRx_ReadReg(UINTPTR BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>, <a class="el" href="xv__hdmirx_8c.html#a0ede81f7ab3357d5fe81c8df0f125e27">XV_HdmiRx_DdcGetEdidWords()</a>, <a class="el" href="xv__hdmirx_8h.html#a257f8ee397eb2b80be3bd776c4120320">XV_HdmiRx_DdcGetHdcpReadMessageBufferWords()</a>, <a class="el" href="xv__hdmirx_8h.html#a5d6a4d5464644a04891aaa68c3343edb">XV_HdmiRx_DdcGetHdcpWriteMessageBufferWords()</a>, <a class="el" href="xv__hdmirx_8h.html#a17547b4a343f0d8a57728948d063ef90">XV_HdmiRx_DdcHdcpReadData()</a>, <a class="el" href="xv__hdmirx_8h.html#a6118306bb3bc6821b5a87640a34cafcc">XV_HdmiRx_DdcIsHdcpReadMessageBufferEmpty()</a>, <a class="el" href="xv__hdmirx_8h.html#a974d5daca9913663c9752972d3953ba4">XV_HdmiRx_DdcIsHdcpWriteMessageBufferEmpty()</a>, <a class="el" href="xv__hdmirx_8h.html#ae3dcd032d351867697f19280fdeb1eeb">XV_HdmiRx_GetAcrCts()</a>, <a class="el" href="xv__hdmirx_8h.html#a0b9483d540e72c619bcc9ba5d516ebe8">XV_HdmiRx_GetAcrN()</a>, <a class="el" href="xv__hdmirx_8h.html#a4b2650f744a2a244482124697e632863">XV_HdmiRx_GetAviColorSpace()</a>, <a class="el" href="xv__hdmirx_8h.html#afaa89bbc453b2d7e1446140c73b7baee">XV_HdmiRx_GetAviVic()</a>, <a class="el" href="xv__hdmirx_8h.html#a87e0904b6a6167f3cde2e7fcc0843e1d">XV_HdmiRx_GetGcpColorDepth()</a>, <a class="el" href="xv__hdmirx_8h.html#aad02ea3d99f0ac3a7f4a0b18f88d62e8">XV_HdmiRx_GetLinkStatus()</a>, <a class="el" href="xv__hdmirx_8h.html#a36bca352ee91492da1392cae5ddcfa6c">XV_HdmiRx_GetTmdsClockRatio()</a>, <a class="el" href="xv__hdmirx_8h.html#a6f74899b52dfbb8e0e554bbdea04bd29">XV_HdmiRx_GetVideoProperties()</a>, <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>, <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>, <a class="el" href="xv__hdmirx_8h.html#a70bb5419e7285a268518668fda1d70cd">XV_HdmiRx_IsLinkStatusErrMax()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

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<a class="anchor" id="a332d931d6e1f46b32ecd1e4ef6229dae"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_SCDC_BRAM_OFFSET&#160;&#160;&#160;0x138</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>SCDC BRAM Offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx_8h.html#a1f3aba5c534ac78d74315a5f8bd6fa62">XV_HdmiRx_WriteScdcRegister()</a>.</p>

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<a class="anchor" id="a58ff62ffa6d07e198733b7ef576f2ac3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_SHIFT_16&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 shift value </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

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<a class="anchor" id="acc84ec76d1d4480d32bfcc0a6d36c9cf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CNT_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Counter Register offset. </p>

</div>
</div>
<a class="anchor" id="a418a4e82c61dfecb6fba2ae6fa645cc5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a32d7a633d71248f00c6c3a0c4cc45709"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="aadd3b41587950a820be6cdacc340bef3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control register offset. </p>

</div>
</div>
<a class="anchor" id="a1583ebb7279d885effb9fcdd993210fd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Run mask. </p>

</div>
</div>
<a class="anchor" id="acfb602db80f1b5565752761a4e1d3203"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="a0cf543f243de78f481f48c4639ac1f94"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Identification register offset. </p>

</div>
</div>
<a class="anchor" id="a8561f573c1afd06984ecd2fc0c3ffd3b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_STA_CNT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status counter Event mask. </p>

</div>
</div>
<a class="anchor" id="aa15bfe16e6a4aa77cc680ea22cd03c9c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a8a2a11c35b8b89348b193ce2273b0044"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

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</div>
<a class="anchor" id="a03680168612106285110985639ce8aaf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VER_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VER_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VER Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="a09dd02e2eec9abeece66f495f3f1624d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VER_VERSION_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VER_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VER Version Register * offset. </p>

</div>
</div>
<a class="anchor" id="a8e1330cc6542ff96733cb7f7e29465fc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_ACT_LIN_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Active Lines Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a680b488ede6d6a8ec9d730deff7559e8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_ACT_PIX_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Active Pixels Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="acbbb7da3f11adf6adaeb53543411f7b2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Clear Register offset. </p>

</div>
</div>
<a class="anchor" id="a79e70fa96e30594b7f96286c786a8ab6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_FIELD_POL_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control field polarity mask. </p>

</div>
</div>
<a class="anchor" id="a742400164fe40d8d72d309affc8d2bf2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="acc56d3a8152c535ce8783d2ff82f4227"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Register offset. </p>

</div>
</div>
<a class="anchor" id="af9e3cef6d874c106289bb83133776baf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Run mask. </p>

</div>
</div>
<a class="anchor" id="af82aee3a907bcd6e34308267e8d67014"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Set Register offset. </p>

</div>
</div>
<a class="anchor" id="a52ae42852070a50b3a7229c2f66462bd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_SYNC_LOSS_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control field polarity mask. </p>

</div>
</div>
<a class="anchor" id="ab645b5a6852d39b83d669dd90fb5d383"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_TIMEBASE_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control timebase shift. </p>

</div>
</div>
<a class="anchor" id="a829444947a7549a148b9f77c162def4f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_TIMERBASE_MASK&#160;&#160;&#160;0xffffff</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control timebase mask. </p>

</div>
</div>
<a class="anchor" id="ae639e59a8ebf41da214a1de1246feae3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_HBP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(14*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Horizontal Back Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a9d1c2a6712699269f8e69dd2c576a3eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_HFP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Horizontal Front Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a18b3fcc81e0b4ebffe5d03b93b9e3a92"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_HSW_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Horizontal Sync Width Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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          <td class="memname">#define XV_HDMIRX_VTD_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(0*4))</td>
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<p>VTD Identification Register offset. </p>

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          <td class="memname">#define XV_HDMIRX_VTD_STA_FMT_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
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<p>VTD Status Format mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="abb3320c46658b4aaa9faa3c78f535fd1"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_STA_HS_POL_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
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<p>VTD Status Hsync Polarity mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="aeb5ef898fca55fa90ee72374af67f0ae"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
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<p>VTD Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

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          <td class="memname">#define XV_HDMIRX_VTD_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(4*4))</td>
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<p>VTD Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>, and <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

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          <td class="memname">#define XV_HDMIRX_VTD_STA_SYNC_LOSS_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
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<p>VTD Status Sync Loss mask. </p>

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<a class="anchor" id="a1f2b2eef2e119965b72bc6ba2d631cb8"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_STA_TIMEBASE_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
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<p>VTD Status timebase event mask. </p>

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<a class="anchor" id="aa003ad3deba710d8250e4d09c3d706a4"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_STA_VS_POL_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
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<p>VTD Status Vsync Polarity mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="a760c24aa9d33dd2727c6106537c4723d"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_TOT_LIN_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(7*4))</td>
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<p>VTD Total Lines Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="ada7dd9b96b61f5400488120a035a733c"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_TOT_PIX_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(5*4))</td>
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<p>VTD Total Pixels Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="a0f25a70ae387411851a4e26d62c4a42a"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_VBP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(12*4))</td>
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<p>VTD Vertical Back Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="a7976bef95da52ceaf075d949bbf95fe4"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_VFP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(11*4))</td>
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<p>VTD Vertical Front Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="a38aa5d3cc486342d8414cccece29d578"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_VSW_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(9*4))</td>
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<p>VTD Vertical Sync Width Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="a407dbf36f2752c30d265e3a8a25d29fe"></a>
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          <td class="memname">#define XV_HdmiRx_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmirx__hw_8h.html#aed43ceb241150a4219514143f8473a4d">XV_HdmiRx_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td>
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<p>This macro writes a value to a HDMI RX register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI RX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx__hw_8h.html#a407dbf36f2752c30d265e3a8a25d29fe" title="This macro writes a value to a HDMI RX register. ">XV_HdmiRx_WriteReg(UINTPTR BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a35f897045a59a453923ce248b1eb8183">XV_HdmiRx_CfgInitialize()</a>, <a class="el" href="xv__hdmirx_8h.html#ac1b7e27bd3874e33114b2e0210f54d4c">XV_HdmiRx_ClearLinkStatus()</a>, <a class="el" href="xv__hdmirx_8h.html#a7d5ad8989577d890a1df04c252daa478">XV_HdmiRx_DdcHdcpSetAddress()</a>, <a class="el" href="xv__hdmirx_8h.html#a7cc9095feabfbd561eeb22c90f793a7b">XV_HdmiRx_DdcHdcpWriteData()</a>, <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>, <a class="el" href="xv__hdmirx_8h.html#ac7e573a18cc3fce40df684e53433ac3b">XV_HdmiRx_EXT_SYSRST()</a>, <a class="el" href="xv__hdmirx_8h.html#aee47f6ad9b1b97962b16b90ccd7ee851">XV_HdmiRx_EXT_VRST()</a>, <a class="el" href="xv__hdmirx_8h.html#ae24d729d135dccfda7ff0c9757e36181">XV_HdmiRx_INT_LRST()</a>, <a class="el" href="xv__hdmirx_8h.html#a9075952d1ee753ba1bf92ea8643359f5">XV_HdmiRx_INT_VRST()</a>, <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>, <a class="el" href="xv__hdmirx_8h.html#a8601d159dffdd4fd77d05d248b366a54">XV_HdmiRx_SetHpd()</a>, <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>, and <a class="el" href="xv__hdmirx_8h.html#a1f3aba5c534ac78d74315a5f8bd6fa62">XV_HdmiRx_WriteScdcRegister()</a>.</p>

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